Invention Grant
- Patent Title: Method for gate stack formation and etching
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Application No.: US16782680Application Date: 2020-02-05
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Publication No.: US12009430B2Publication Date: 2024-06-11
- Inventor: Sergey Voronin , Christopher Catano , Sang Cheol Han , Shyam Sridhar , Yusuke Yoshida , Christopher Talone , Alok Ranjan
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Egan, Enders & Huston LLP.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/02 ; H01L21/3065 ; H01L21/3213 ; H01L29/66

Abstract:
Residue at the base of a feature in a substrate to be etched is limited so that improved profiles may be obtained when forming vertical, narrow pitch, high aspect ratio features, for example fin field effect transistor (FinFET) gates. A thin bottom layer of the feature is formed of a different material than the main layer of the feature. The bottom material may be comprised of a material that preferentially etches and/or preferentially oxidizes as compared to the main layer. The bottom layer may comprise silicon germanium. The preferential etching characteristics may provide a process in which un-etched residuals do not remain. Even if residuals remain, after etch of the feature, an oxidation process may be performed. Enhanced oxidation rates of the bottom material allow any remaining residual to be oxidized. Plasma oxidation may be used. The oxidized material may then be removed by utilizing standard oxide removal mechanisms.
Public/Granted literature
- US20200273992A1 METHOD FOR GATE STACK FORMATION AND ETCHING Public/Granted day:2020-08-27
Information query
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