Invention Grant
- Patent Title: High density logic formation using multi-dimensional laser annealing
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Application No.: US17632212Application Date: 2020-07-29
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Publication No.: US12087640B2Publication Date: 2024-09-10
- Inventor: H. Jim Fulford , Mark I. Gardner , Jeffrey Smith , Lars Liebmann , Daniel Chanemougame
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- International Application: PCT/US2020/043986 2020.07.29
- International Announcement: WO2021/025914A 2021.02.11
- Date entered country: 2022-02-01
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/822 ; H01L21/8238 ; H01L27/092 ; H01L29/66 ; H01L29/786

Abstract:
A method of forming transistor devices is described that includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of epitaxial film adaptable for forming channels of field effect transistors, depositing a first insulator layer on the first transistor plane, depositing a first layer of polycrystalline silicon on the first insulator layer, annealing the first layer of polycrystalline silicon using laser heating. The laser heating increases grain size of the first layer of polycrystalline silicon. The method further includes forming a second transistor plane on the first layer of polycrystalline silicon, the second transistor plane being adaptable for forming channels of field effect transistors, depositing a second insulator layer on the second transistor plane, depositing a second layer of polycrystalline silicon on the second insulator layer, and annealing the second layer of polycrystalline silicon using laser heating.
Public/Granted literature
- US20220277957A1 HIGH DENSITY LOGIC FORMATION USING MULTI-DIMENSIONAL LASER ANNEALING Public/Granted day:2022-09-01
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