A semiconductor memory structure includes a semiconductor substrate, a bit line disposed on the semiconductor substrate, a dielectric liner disposed on a sidewall of the bit line and a capacitor contact disposed on a side of the bit line. The dielectric liner includes a first nitride liner disposed on a sidewall of the bit line, an oxide liner disposed on a sidewall of the first nitride liner, and a second nitride liner disposed on a sidewall of the oxide liner. The capacitor contact includes a semiconductor plug disposed on the semiconductor substrate, a metal plug disposed on the semiconductor plug, a metal silicide liner including a sidewall portion and a bottom portion extending along the sidewall and the bottom of the metal plug respectively, and a nitride layer disposed on the metal silicide liner. The sidewall portion is disposed directly above the second nitride liner.