公开(公告)号：US11923449B2

公开(公告)日：2024-03-05

申请号：US17739210

申请日：2022-05-09

Applicant: Winbond Electronics Corp.

Inventor： Hao-Chuan Chang ,  Kai Jen

IPC: H01L29/66 ,  H01L21/285 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/778 ,  H10B12/00

CPC classification number: H01L29/7789 ,  H01L21/28581 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786 ,  H10B12/053 ,  H10B12/34

Abstract: A manufacturing method for a semiconductor device is provided. The method includes: forming a recess at a top surface of a substrate; forming a channel layer and a barrier layer in order, to conformally cover surfaces of the recess; filling up the recess with a conductive material; removing a top portion of the conductive material, such that a lower portion of the conductive material remained in the recess forms a gate electrode; and forming an insulating structure on the gate electrode. A hetero junction formed at an interface of the channel layer and the barrier layer is external to the substrate, and a two dimensional electron gas or a two dimensional hole gas is induced along the hetero junction external to the substrate.

公开(公告)号：US11430792B2

公开(公告)日：2022-08-30

申请号：US16924235

申请日：2020-07-09

Applicant: Winbond Electronics Corp.

Inventor： Kai Jen ,  Hao-Chuan Chang

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/66

Abstract: Provided is a DRAM including a substrate, first bit line structures, second bit line structures, and word line structures. The substrate has active regions each including pillar structures arranged along a first direction. Two first bit line structures extended along the first direction and buried in the substrate are disposed between the active regions arranged along a second direction. Each second bit line structure is located between the pillar structures and extended through the active regions along the second direction to be disposed on the first bit line structures and electrically connected to the first bit line structures. The word line structures are disposed on and spaced apart from the second bit line structures. Each word line structure extended along the second direction is located between the pillar structures and passes through the active regions arranged along the second direction. A manufacturing method of the DRAM is also provided.

公开(公告)号：US20210013209A1

公开(公告)日：2021-01-14

申请号：US16924235

申请日：2020-07-09

Applicant: Winbond Electronics Corp.

Inventor： Kai Jen ,  Hao-Chuan Chang

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/66

Abstract: Provided is a DRAM including a substrate, first bit line structures, second bit line structures, and word line structures. The substrate has active regions each including pillar structures arranged along a first direction. Two first bit line structures extended along the first direction and buried in the substrate are disposed between the active regions arranged along a second direction. Each second bit line structure is located between the pillar structures and extended through the active regions along the second direction to be disposed on the first bit line structures and electrically connected to the first bit line structures. The word line structures are disposed on and spaced apart from the second bit line structures. Each word line structure extended along the second direction is located between the pillar structures and passes through the active regions arranged along the second direction. A manufacturing method of the DRAM is also provided.

公开(公告)号：US11751380B2

公开(公告)日：2023-09-05

申请号：US17412992

申请日：2021-08-26

Applicant: Winbond Electronics Corp.

Inventor： Hao-Chuan Chang ,  Jiun-Sheng Yang

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/482

Abstract: A semiconductor memory structure includes a semiconductor substrate, a bit line disposed on the semiconductor substrate, and a capacitor contact disposed on the side of the bit line. The capacitor contact includes a semiconductor plug disposed on the semiconductor substrate, a metal plug disposed on the semiconductor plug, a metal silicide liner extending along the sidewalls and bottom of the metal plug, and a nitride layer disposed on the metal silicide liner. The top surface of the metal silicide liner is lower than the top surface of the metal plug. The nitride layer surrounds the top portion of the metal plug.

公开(公告)号：US11665879B2

公开(公告)日：2023-05-30

申请号：US17864411

申请日：2022-07-14

Applicant: Winbond Electronics Corp.

Inventor： Kai Jen ,  Hao-Chuan Chang

IPC: H01L21/74 ,  H01L29/78 ,  H01L29/66

CPC classification number: H10B12/02 ,  H01L29/66666 ,  H01L29/7827 ,  H10B12/01 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/09 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

Abstract: A method of manufacturing a DRAM includes proving a substrate having active regions. First bit line structures are buried in the substrate. Each of first bit line structures extends along a first direction. Every two of the first bit line structures are disposed between two neighboring ones of the active regions arranged along a second direction. A plurality of pillar structures are formed arranged along the first direction by dividing each of the active regions. Second bit line structures are formed. Each of the second bit line structures is located between the pillar structures of a corresponding one of the active regions and extends through the corresponding one of the active regions along the second direction to be disposed on the first bit line structures at two sides of the corresponding one of the active regions and be electrically connected to the first bit line structures below.

公开(公告)号：US20250098250A1

公开(公告)日：2025-03-20

申请号：US18780512

申请日：2024-07-23

Applicant: Winbond Electronics Corp.

Inventor： Noriaki Ikeda ,  Chun-Sheng Yang ,  Hao-Chuan Chang

IPC: H01L29/161 ,  H01L21/02 ,  H01L29/423

Abstract: A semiconductor structure including a substrate, a first electrode, a first dielectric layer, and a second electrode is provided. The first electrode is located on the substrate. The first electrode is pillar-shaped. The first dielectric layer is located on the first electrode. The second electrode is located on the first dielectric layer. The second electrode includes a first silicon germanium (SiGe) layer and a second SiGe layer. The first SiGe layer is located on the first dielectric layer. The second SiGe layer is located on the first SiGe layer. A content of germanium in the second SiGe layer is greater than a content of germanium in the first SiGe layer.

公开(公告)号：US20240155835A1

公开(公告)日：2024-05-09

申请号：US18473317

申请日：2023-09-25

Applicant: Winbond Electronics Corp.

Inventor： Hao-Chuan Chang

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/033 ,  H10B12/315 ,  H10B12/482

Abstract: A DRAM including a substrate, a plurality of bit line structures, and a contact is provided. The substrate has an active area. The bit line structures are arranged on the substrate, and each bit line structure at least includes a conductive structure, an insulating cover layer and a spacer. The insulating cover layer is arranged on the conductive structure. The spacer is arranged on the side wall of the conductive structure and the side wall of the insulating cover layer. The conductive structure is configured to be electrically connected to the active area. The contact is located between the bit line structures, and at least a part of the contact extends below the spacer of one of the bit line structures.

公开(公告)号：US11367787B2

公开(公告)日：2022-06-21

申请号：US16681704

申请日：2019-11-12

Applicant: Winbond Electronics Corp.

Inventor： Hao-Chuan Chang ,  Kai Jen

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L27/108 ,  H01L21/285 ,  H01L29/66

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first channel layer, a first barrier layer, a gate electrode and an insulating structure. The substrate has a recess, and the first channel layer, the first barrier layer, the gate electrode and the insulating structure are disposed in the recess. The first channel layer covers a surface of the recess. The first barrier layer is disposed on a surface of the first channel layer. A surface of a bottom portion of the first barrier layer is covered by the gate electrode, and a top surface of the gate electrode is lower than a topmost surface of the substrate. Surfaces of the gate electrode and a top portion of the first barrier layer are covered by the insulating structure.

公开(公告)号：US12302546B2

公开(公告)日：2025-05-13

申请号：US17891925

申请日：2022-08-19

Applicant: Winbond Electronics Corp.

Inventor： Hao-Chuan Chang

IPC: H10B12/00 ,  G11C5/06

Abstract: A semiconductor memory structure includes a semiconductor substrate, a bit line disposed on the semiconductor substrate, a dielectric liner disposed on a sidewall of the bit line and a capacitor contact disposed on a side of the bit line. The dielectric liner includes a first nitride liner disposed on a sidewall of the bit line, an oxide liner disposed on a sidewall of the first nitride liner, and a second nitride liner disposed on a sidewall of the oxide liner. The capacitor contact includes a semiconductor plug disposed on the semiconductor substrate, a metal plug disposed on the semiconductor plug, a metal silicide liner including a sidewall portion and a bottom portion extending along the sidewall and the bottom of the metal plug respectively, and a nitride layer disposed on the metal silicide liner. The sidewall portion is disposed directly above the second nitride liner.

公开(公告)号：US20220344342A1

公开(公告)日：2022-10-27

申请号：US17864411

申请日：2022-07-14

Applicant: Winbond Electronics Corp.

Inventor： Kai Jen ,  Hao-Chuan Chang

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/66

Abstract: A method of manufacturing a DRAM includes proving a substrate having active regions. First bit line structures are buried in the substrate. Each of first bit line structures extends along a first direction. Every two of the first bit line structures are disposed between two neighboring ones of the active regions arranged along a second direction. A plurality of pillar structures are formed arranged along the first direction by dividing each of the active regions. Second bit line structures are formed. Each of the second bit line structures is located between the pillar structures of a corresponding one of the active regions and extends through the corresponding one of the active regions along the second direction to be disposed on the first bit line structures at two sides of the corresponding one of the active regions and be electrically connected to the first bit line structures below.