Invention Application
US20150280746A1 Low Latency Serial Data Encoding Scheme For Enhanced Burst Error Immunity and Long Term Reliability 有权
低延迟串行数据编码方案,用于增强突发误码抗扰度和长期可靠性

Low Latency Serial Data Encoding Scheme For Enhanced Burst Error Immunity and Long Term Reliability
Abstract:
A high performance computing system and method communicate data packets between computing nodes on a multi-lane communications link using a modified header bit encoding. Each data packet is provided with flow control information and error detection information, then divided into per-lane payloads. Sync header bits for each payload are added to the payloads in non-adjacent locations, thereby decreasing the probability that a single correlated burst error will invert both header bits. The encoded blocks that include the payload and the interspersed header bits are then simultaneously transmitted on the multiple lanes for reception, error detection, and reassembly by a receiving computing node.
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