Low latency serial data encoding scheme for enhanced burst error immunity and long term reliability
    2.
    发明授权
    Low latency serial data encoding scheme for enhanced burst error immunity and long term reliability 有权
    低延迟串行数据编码方案,提高突发差错抗扰度和长期可靠性

    公开(公告)号:US09252812B2

    公开(公告)日:2016-02-02

    申请号:US14229796

    申请日:2014-03-28

    Abstract: A high performance computing system and method communicate data packets between computing nodes on a multi-lane communications link using a modified header bit encoding. Each data packet is provided with flow control information and error detection information, then divided into per-lane payloads. Sync header bits for each payload are added to the payloads in non-adjacent locations, thereby decreasing the probability that a single correlated burst error will invert both header bits. The encoded blocks that include the payload and the interspersed header bits are then simultaneously transmitted on the multiple lanes for reception, error detection, and reassembly by a receiving computing node.

    Abstract translation: 高性能计算系统和方法使用修改的报头位编码在多通道通信链路上的计算节点之间传送数据分组。 每个数据包都提供流量控制信息和错误检测信息,然后划分为每通道有效载荷。 每个有效载荷的同步头位被添加到非相邻位置中的有效载荷,从而降低单个相关突发错误将颠倒两个标题位的概率。 然后,在多个通道上同时发送包含有效载荷和散布的报头位的编码块,以便接收计算节点进行接收,错误检测和重组。

    Low Latency Serial Data Encoding Scheme For Enhanced Burst Error Immunity and Long Term Reliability
    3.
    发明申请
    Low Latency Serial Data Encoding Scheme For Enhanced Burst Error Immunity and Long Term Reliability 有权
    低延迟串行数据编码方案,用于增强突发误码抗扰度和长期可靠性

    公开(公告)号:US20150280746A1

    公开(公告)日:2015-10-01

    申请号:US14229796

    申请日:2014-03-28

    Abstract: A high performance computing system and method communicate data packets between computing nodes on a multi-lane communications link using a modified header bit encoding. Each data packet is provided with flow control information and error detection information, then divided into per-lane payloads. Sync header bits for each payload are added to the payloads in non-adjacent locations, thereby decreasing the probability that a single correlated burst error will invert both header bits. The encoded blocks that include the payload and the interspersed header bits are then simultaneously transmitted on the multiple lanes for reception, error detection, and reassembly by a receiving computing node.

    Abstract translation: 高性能计算系统和方法使用修改的报头位编码在多通道通信链路上的计算节点之间传送数据分组。 每个数据包都提供流量控制信息和错误检测信息,然后划分为每通道有效载荷。 每个有效载荷的同步头位被添加到非相邻位置中的有效载荷,从而降低单个相关突发错误将颠倒两个标题位的概率。 然后,在多个通道上同时发送包含有效载荷和散布的报头位的编码块,以便接收计算节点进行接收,错误检测和重组。

    Method and System for High Speed Data Links
    4.
    发明申请
    Method and System for High Speed Data Links 审中-公开
    高速数据链接方法与系统

    公开(公告)号:US20160373557A1

    公开(公告)日:2016-12-22

    申请号:US14742007

    申请日:2015-06-17

    Abstract: Various embodiments improve the operation of computers by providing methods of transmitting data with low latency and high bandwidth. Data may be transmitted in a packet composed of data flits, the data flits having at least two different formats configured to implement different communication protocols. In some embodiments, a given flit may be transmitted using two different modulation methods, with a first part of the flit transmitted using a first modulation method, such as a binary method, and a second part of the flit using a higher-order modulation method.

    Abstract translation: 各种实施例通过提供以低延迟和高带宽传输数据的方法来改善计算机的操作。 数据可以在由数据流组成的分组中发送,数据闪存具有被配置为实现不同通信协议的至少两种不同格式。 在一些实施例中,可以使用两种不同的调制方法来发送给定的小区,其中使用诸如二进制方法的第一调制方法传输的小区的第一部分,以及使用较高阶调制方法的小区的第二部分 。

    High Speed Serial Link In-Band Lane Fail Over for RAS and Power Management
    5.
    发明申请
    High Speed Serial Link In-Band Lane Fail Over for RAS and Power Management 有权
    RAS和电源管理的高速串行带内通道故障切换

    公开(公告)号:US20150278040A1

    公开(公告)日:2015-10-01

    申请号:US14224795

    申请日:2014-03-25

    Abstract: A system and method provide a communications link having a plurality of lanes, and an in-band, real-time physical layer protocol that keeps all lanes on-line, while failing lanes are removed, for continuous service during fail over operations. Lane status is monitored real-time at the physical layer receiver, where link error rate, per lane error performance, and other channel metrics are known. If a lane failure is established, a single round trip request/acknowledge protocol exchange with the remote port completes the fail over. If a failing lane meets an acceptable performance level, it remains on-line during the round trip exchange, resulting in uninterrupted link service. Lanes may be brought in or out of service to meet reliability, availability, and power consumption goals.

    Abstract translation: 系统和方法提供具有多个通道的通信链路,以及带内实时物理层协议,其在故障切换操作期间连续服务,保持所有车道在线,同时消除故障车道。 在物理层接收机处实时监控通道状态,其中链路错误率,每通道错误性能和其他信道度量是已知的。 如果建立通道故障,则与远程端口的单一往返请求/确认协议交换完成故障切换。 如果失败的车道达到可接受的性能水平,则在往返交换期间保持在线,导致不间断的链路服务。 车道可能被带入或不服务,以满足可靠性,可用性和功耗目标。

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