公开(公告)号：US09252812B2

公开(公告)日：2016-02-02

申请号：US14229796

申请日：2014-03-28

Applicant: Silicon Graphics International Corp.

Inventor： Mark Ronald Sikkink ,  John Francis De Ryckere

IPC: H03M13/00 ,  H03M13/17 ,  H03M13/09 ,  H04L1/00 ,  H03M13/11

CPC classification number: H03M13/17 ,  H03M13/09 ,  H03M13/11 ,  H04L1/0057 ,  H04L1/0061 ,  H04L1/0079 ,  H04L1/0083 ,  H04L25/14 ,  H04L25/4908

Abstract: A high performance computing system and method communicate data packets between computing nodes on a multi-lane communications link using a modified header bit encoding. Each data packet is provided with flow control information and error detection information, then divided into per-lane payloads. Sync header bits for each payload are added to the payloads in non-adjacent locations, thereby decreasing the probability that a single correlated burst error will invert both header bits. The encoded blocks that include the payload and the interspersed header bits are then simultaneously transmitted on the multiple lanes for reception, error detection, and reassembly by a receiving computing node.

Abstract translation: 高性能计算系统和方法使用修改的报头位编码在多通道通信链路上的计算节点之间传送数据分组。 每个数据包都提供流量控制信息和错误检测信息，然后划分为每通道有效载荷。 每个有效载荷的同步头位被添加到非相邻位置中的有效载荷，从而降低单个相关突发错误将颠倒两个标题位的概率。 然后，在多个通道上同时发送包含有效载荷和散布的报头位的编码块，以便接收计算节点进行接收，错误检测和重组。

公开(公告)号：US20150280746A1

公开(公告)日：2015-10-01

申请号：US14229796

申请日：2014-03-28

Applicant: Silicon Graphics International Corp.

Inventor： Mark Ronald Sikkink ,  John Francis De Ryckere

IPC: H03M13/17 ,  H03M13/09

CPC classification number: H03M13/17 ,  H03M13/09 ,  H03M13/11 ,  H04L1/0057 ,  H04L1/0061 ,  H04L1/0079 ,  H04L1/0083 ,  H04L25/14 ,  H04L25/4908

Abstract: A high performance computing system and method communicate data packets between computing nodes on a multi-lane communications link using a modified header bit encoding. Each data packet is provided with flow control information and error detection information, then divided into per-lane payloads. Sync header bits for each payload are added to the payloads in non-adjacent locations, thereby decreasing the probability that a single correlated burst error will invert both header bits. The encoded blocks that include the payload and the interspersed header bits are then simultaneously transmitted on the multiple lanes for reception, error detection, and reassembly by a receiving computing node.

Abstract translation: 高性能计算系统和方法使用修改的报头位编码在多通道通信链路上的计算节点之间传送数据分组。 每个数据包都提供流量控制信息和错误检测信息，然后划分为每通道有效载荷。 每个有效载荷的同步头位被添加到非相邻位置中的有效载荷，从而降低单个相关突发错误将颠倒两个标题位的概率。 然后，在多个通道上同时发送包含有效载荷和散布的报头位的编码块，以便接收计算节点进行接收，错误检测和重组。

公开(公告)号：US20150278040A1

公开(公告)日：2015-10-01

申请号：US14224795

申请日：2014-03-25

Applicant: Silicon Graphics International Corp.

Inventor： Mark Ronald Sikkink ,  John Francis De Ryckere ,  Joseph Martin Placek ,  Karen Rae Beighley

IPC: G06F11/20 ,  G06F13/40

CPC classification number: G06F13/4022 ,  G06F11/2007 ,  G06F2201/81 ,  G06F2201/85 ,  H04L1/1848 ,  H04L1/20 ,  H04L1/22 ,  H04L2001/0096

Abstract: A system and method provide a communications link having a plurality of lanes, and an in-band, real-time physical layer protocol that keeps all lanes on-line, while failing lanes are removed, for continuous service during fail over operations. Lane status is monitored real-time at the physical layer receiver, where link error rate, per lane error performance, and other channel metrics are known. If a lane failure is established, a single round trip request/acknowledge protocol exchange with the remote port completes the fail over. If a failing lane meets an acceptable performance level, it remains on-line during the round trip exchange, resulting in uninterrupted link service. Lanes may be brought in or out of service to meet reliability, availability, and power consumption goals.

Abstract translation: 系统和方法提供具有多个通道的通信链路，以及带内实时物理层协议，其在故障切换操作期间连续服务，保持所有车道在线，同时消除故障车道。 在物理层接收机处实时监控通道状态，其中链路错误率，每通道错误性能和其他信道度量是已知的。 如果建立通道故障，则与远程端口的单一往返请求/确认协议交换完成故障切换。 如果失败的车道达到可接受的性能水平，则在往返交换期间保持在线，导致不间断的链路服务。 车道可能被带入或不服务，以满足可靠性，可用性和功耗目标。