Invention Application
US20170005041A1 METHOD TO REDUCE TRAP-INDUCED CAPACITANCE IN INTERCONNECT DIELECTRIC BARRIER STACK
审中-公开
减少互连电介质堆叠中的陷波电容的方法
- Patent Title: METHOD TO REDUCE TRAP-INDUCED CAPACITANCE IN INTERCONNECT DIELECTRIC BARRIER STACK
- Patent Title (中): 减少互连电介质堆叠中的陷波电容的方法
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Application No.: US15186436Application Date: 2016-06-18
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Publication No.: US20170005041A1Publication Date: 2017-01-05
- Inventor: He REN , Mehul B. NAIK , Yong CAO , Yana CHENG , Weifeng YE
- Applicant: Applied Materials, Inc.
- Main IPC: H01L23/532
- IPC: H01L23/532 ; H01L21/02 ; H01L23/528 ; H01L21/768
Abstract:
The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.
Public/Granted literature
- US10170299B2 Method to reduce trap-induced capacitance in interconnect dielectric barrier stack Public/Granted day:2019-01-01
Information query
IPC分类:
