公开(公告)号：US20240379420A1

公开(公告)日：2024-11-14

申请号：US18781633

申请日：2024-07-23

Applicant: APPLIED MATERIALS, INC.

Inventor： Shi YOU ,  He REN ,  Naomi YOSHIDA ,  Nikolaos BEKIARIS ,  Mehul NAIK ,  Martin Jay SEAMONS ,  Jingmei LIANG ,  Mei-Yee SHEK

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/67

Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material

公开(公告)号：US20190157145A1

公开(公告)日：2019-05-23

申请号：US16252100

申请日：2019-01-18

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Feiyue MA ,  Yu LEI ,  Kai WU ,  Mehul B. NAIK ,  Zhiyuan WU ,  Vikash BANTHIA ,  Hua AI

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L23/522

Abstract: Interconnects and methods for forming interconnects are described and disclosed herein. The interconnect contains a stack formed on a substrate having a via and a trench formed therein, a first metal formed from a first material of a first type deposited in the via, and a second metal formed from a second material of a second type deposited in the trench.

公开(公告)号：US20190051557A1

公开(公告)日：2019-02-14

申请号：US16102543

申请日：2018-08-13

Applicant: Applied Materials, Inc.

Inventor： Bencherki MEBARKI ,  Sean S. KANG ,  Keith Tatseun WONG ,  He REN ,  Mehul B. NAIK ,  Ellie Y. YIEH ,  Srinivas D. NEMANI

IPC: H01L21/768 ,  H01L23/532

Abstract: Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, and grain boundaries from interconnects formed on the substrate. The method includes heating the substrate in an environment pressurized at supra-atmospheric pressure. In one example, the substrate may be heated in a hydrogen-containing atmosphere.

公开(公告)号：US20170005041A1

公开(公告)日：2017-01-05

申请号：US15186436

申请日：2016-06-18

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Mehul B. NAIK ,  Yong CAO ,  Yana CHENG ,  Weifeng YE

IPC: H01L23/532 ,  H01L21/02 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L21/02167 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/76826 ,  H01L21/76832

Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.

Abstract translation: 本公开提供了形成在衬底上的互连和用于在衬底上形成互连的方法。 在一个实施例中，用于在衬底上形成互连的方法包括在衬底上沉积阻挡层，在阻挡层上沉积过渡层，以及在过渡层上沉积蚀刻停止层，其中过渡层共享共同 元件，并且其中所述过渡层与所述蚀刻停止层共享公共元件。

公开(公告)号：US20160211172A1

公开(公告)日：2016-07-21

申请号：US15084104

申请日：2016-03-29

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Mehul B. NAIK

IPC: H01L21/768 ,  H01L21/3105 ,  H01L21/764 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/02126 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/32136 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76889

Abstract: Embodiments described herein relate to methods for forming an air gap interconnect. A metal spacer layer is conformally deposited on a substrate having mandrel structures formed thereon. The metal spacer layer is etched to form spacer features and the mandrel structures are removed from the substrate. Various other dielectric deposition, patterning and etching steps may be performed to desirably pattern materials present on the substrate. Ultimately, a trench is formed between adjacent spacer features and a capping layer is deposited over the trench to form an air gap between the adjacent spacer features. For packaging purposes, an interconnect via may be configured to contact at least one of the spacer features adjacent the air gap.

公开(公告)号：US20230260825A1

公开(公告)日：2023-08-17

申请号：US17670777

申请日：2022-02-14

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Houssam LAZKANI ,  Raman GAIRE ,  Mehul NAIK ,  Kuan-Ting LIU

IPC: H01L21/74 ,  H01L23/528 ,  H01L21/20 ,  H01L23/535 ,  H01L21/02

CPC classification number: H01L21/743 ,  H01L23/5286 ,  H01L21/2022 ,  H01L23/535 ,  H01L21/02016

Abstract: A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.

公开(公告)号：US20210317580A1

公开(公告)日：2021-10-14

申请号：US16848784

申请日：2020-04-14

Applicant: APPLIED MATERIALS, INC.

Inventor： Shi YOU ,  He REN ,  Naomi YOSHIDA ,  Nikolaos BEKIARIS ,  Mehul NAIK ,  Martin Jay SEAMONS ,  Jingmei LIANG ,  Mei-Yee SHEK

IPC: C23C16/56 ,  H01L21/768

Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material

公开(公告)号：US20190027403A1

公开(公告)日：2019-01-24

申请号：US16140342

申请日：2018-09-24

Applicant: APPLIED MATERIALS, INC.

Inventor： Sree Rangasai V. KESAPRAGADA ,  Kevin MORAES ,  Srinivas GUGGILLA ,  He REN ,  Mehul NAIK ,  David THOMPSON ,  Weifeng YE ,  Yana CHENG ,  Yong CAO ,  Xianmin TANG ,  Paul F. MA ,  Deenesh PADHI

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76832 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02178 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

公开(公告)号：US20170162511A1

公开(公告)日：2017-06-08

申请号：US15439145

申请日：2017-02-22

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Mehul B. NAIK ,  Yong CAO ,  Mei-yee SHEK

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L23/53238 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber, wherein the substrate comprises a copper layer having an exposed surface and a low-k dielectric layer having an exposed surface, forming a metal layer over the exposed surface of the copper layer, wherein the exposed surface of the low-k dielectric layer is free from the metal layer, and forming a metal-based dielectric layer over the metal layer and over at least part of the exposed low-k dielectric surface, wherein the metal-based dielectric layer comprises an aluminum compound.

公开(公告)号：US20160017492A1

公开(公告)日：2016-01-21

申请号：US14801348

申请日：2015-07-16

Applicant: Applied Materials, Inc.

Inventor： Bo XIE ,  Alexandros T. DEMOS ,  Vu Ngoc Tran NGUYEN ,  Kelvin CHAN ,  He REN ,  Kang Sub YIM ,  Mehul B. NAIK

IPC: C23C16/48 ,  C23C16/40 ,  C23C16/505 ,  B01J19/12

CPC classification number: C23C16/482 ,  C23C16/401 ,  H01L21/3105 ,  H01L21/76825 ,  H01L21/76829

Abstract: Embodiments described herein provide a method for sealing a porous low-k dielectric film. The method includes forming a sealing layer on the porous low-k dielectric film using a cyclic process. The cyclic process includes repeating a sequence of depositing a sealing layer on the porous low-k dielectric film and treating the sealing layer until the sealing layer achieves a predetermined thickness. The treating of each intermediate sealing layer generates more reactive sites on the surface of each intermediate sealing layer, which improves the quality of the resulting sealing layer.

Abstract translation: 本文所述的实施例提供了一种用于密封多孔低k电介质膜的方法。 该方法包括使用循环过程在多孔低k电介质膜上形成密封层。 循环过程包括重复在多孔低k电介质膜上沉积密封层的顺序并处理密封层，直到密封层达到预定厚度。 每个中间密封层的处理在每个中间密封层的表面上产生更多的反应性位点，这提高了所得密封层的质量。