公开(公告)号：US20240003000A1

公开(公告)日：2024-01-04

申请号：US18201055

申请日：2023-05-23

Applicant: Applied Materials, Inc.

Inventor： Mingwei ZHU ,  Zihao YANG ,  Nag B. PATIBANDLA ,  Ludovic GODET ,  Yong CAO ,  Daniel Lee DIEHL ,  Zhebo CHEN

IPC: C23C14/56 ,  C23C14/06 ,  C23C14/34 ,  H01J37/34

CPC classification number: C23C14/564 ,  C23C14/0641 ,  C23C14/34 ,  H01J2237/24514 ,  H01J37/3441 ,  H01J37/3405 ,  H01J37/3464

Abstract: A structure including a metal nitride layer is formed on a workpiece by pre-conditioning a chamber that includes a metal target by flowing nitrogen gas and an inert gas at a first flow rate ratio into the chamber and igniting a plasma in the chamber before placing the workpiece in the chamber, evacuating the chamber after the preconditioning, placing the workpiece on a workpiece support in the chamber after the preconditioning, and performing physical vapor deposition of a metal nitride layer on the workpiece in the chamber by flowing nitrogen gas and the inert gas at a second flow rate ratio into the chamber and igniting a plasma in the chamber. The second flow rate ratio is less than the first flow rate ratio.

公开(公告)号：US20230335393A1

公开(公告)日：2023-10-19

申请号：US18337319

申请日：2023-06-19

Applicant: Applied Materials, Inc.

Inventor： Chunming ZHOU ,  Jothilingam RAMALINGAM ,  Yong CAO ,  Kevin Vincent MORAES ,  Shane LAVAN

IPC: H01L21/02 ,  H01L21/677

CPC classification number: H01L21/02266 ,  H01L21/67745 ,  H01L21/67742

Abstract: Embodiments of the present disclosure generally relate to methods and apparatus for backside stress engineering of substrates to combat film stresses and bowing issues. In one embodiment, a method of depositing a film layer on a backside of a substrate is provided. The method includes flipping a substrate at a factory interface so that the backside of the substrate is facing up, and transferring the flipped substrate from the factory interface to a physical vapor deposition chamber to deposit a film layer on the backside of the substrate. In another embodiment, an apparatus for depositing a backside film layer on a backside of a substrate, which includes a substrate supporting surface configured to support the substrate at or near the periphery of the substrate supporting surface without contacting an active region on a front side of the substrate.

公开(公告)号：US20220186361A1

公开(公告)日：2022-06-16

申请号：US17121603

申请日：2020-12-14

Applicant: Applied Materials, Inc.

Inventor： Kirankumar Neelasandra SAVANDAIAH ,  Shane LAVAN ,  Sundarapandian Ramalinga Vijayalakshmi REDDY ,  Randal Dean SCHMIEDING ,  Yong CAO

IPC: C23C14/56 ,  C23C14/28

Abstract: Embodiments of process shield for use in process chambers are provided herein. In some embodiments, a process shield for use in a process chamber includes: an annular body having an upper portion and a lower portion extending downward and radially inward from the upper portion, wherein the upper portion includes a plurality of annular trenches on an upper surface thereof and having a plurality of slots disposed therebetween to fluidly couple the plurality of annular trenches, wherein one or more inlets extend from an outer surface of the annular body to an outermost trench of the plurality of annular trenches.

公开(公告)号：US20180142343A1

公开(公告)日：2018-05-24

申请号：US15814497

申请日：2017-11-16

Applicant: APPLIED MATERIALS, INC.

Inventor： Weimin ZENG ,  Yong CAO ,  Daniel Lee DIEHL ,  Huixiong DAI ,  Khoi PHAN ,  Christopher NGAI ,  Rongjun WANG ,  Xianmin TANG

IPC: C23C14/35 ,  C23C14/22 ,  C23C14/14 ,  C23C14/54

CPC classification number: C23C14/35 ,  C23C14/0057 ,  C23C14/042 ,  C23C14/06 ,  C23C14/14 ,  C23C14/228 ,  C23C14/54 ,  H01J37/34 ,  H01J2237/332

Abstract: In some embodiments, a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) forming a plasma from a process gas within a processing region of the physical vapor deposition chamber, wherein the process gas comprises an inert gas and a hydrogen-containing gas to sputter silicon from a surface of a target within the processing region of the physical vapor deposition chamber; and (b) depositing an amorphous silicon layer atop a first layer on the substrate, wherein adjusting the flow rate of the hydrogen containing gas tunes the optical properties of the deposited amorphous silicon layer.

公开(公告)号：US20220415649A1

公开(公告)日：2022-12-29

申请号：US17902357

申请日：2022-09-02

Applicant: Applied Materials, Inc.

Inventor： Chunming ZHOU ,  Jothilingam RAMALINGAM ,  Yong CAO ,  Kevin Vincent MORAES ,  Shane LAVAN

IPC: H01L21/02 ,  H01L21/677

Abstract: Embodiments of the present disclosure generally relate to methods and apparatus for backside stress engineering of substrates to combat film stresses and bowing issues. In one embodiment, a method of depositing a film layer on a backside of a substrate is provided. The method includes flipping a substrate at a factory interface so that the backside of the substrate is facing up, and transferring the flipped substrate from the factory interface to a physical vapor deposition chamber to deposit a film layer on the backside of the substrate. In another embodiment, an apparatus for depositing a backside film layer on a backside of a substrate, which includes a substrate supporting surface configured to support the substrate at or near the periphery of the substrate supporting surface without contacting an active region on a front side of the substrate.

公开(公告)号：US20220301828A1

公开(公告)日：2022-09-22

申请号：US17203786

申请日：2021-03-17

Applicant: Applied Materials, Inc.

Inventor： Wei DOU ,  Yong CAO ,  Mingdong LI ,  Shane LAVAN ,  Jothilingam RAMALINGAM ,  Chengyu LIU

IPC: H01J37/32 ,  C23C14/14 ,  C23C14/06 ,  C23C14/34 ,  C23C14/54

Abstract: Embodiments of methods and apparatus for reducing particle formation in physical vapor deposition (PVD) chambers are provided herein. In some embodiments, a method of reducing particle formation in a PVD chamber includes: performing a plurality of first deposition processes on a corresponding series of substrates disposed on a substrate support in the PVD chamber, wherein the PVD chamber includes a cover ring disposed about the substrate support and having a texturized outer surface, and wherein a silicon nitride (SiN) layer having a first thickness is deposited onto the texturized outer surface during each of the plurality of first deposition processes; and performing a second deposition process on the cover ring between subsets of the plurality of first deposition processes to deposit an amorphous silicon layer having a second thickness onto an underlying silicon nitride (SiN) layer.

公开(公告)号：US20190027403A1

公开(公告)日：2019-01-24

申请号：US16140342

申请日：2018-09-24

Applicant: APPLIED MATERIALS, INC.

Inventor： Sree Rangasai V. KESAPRAGADA ,  Kevin MORAES ,  Srinivas GUGGILLA ,  He REN ,  Mehul NAIK ,  David THOMPSON ,  Weifeng YE ,  Yana CHENG ,  Yong CAO ,  Xianmin TANG ,  Paul F. MA ,  Deenesh PADHI

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76832 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02178 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

公开(公告)号：US20170162511A1

公开(公告)日：2017-06-08

申请号：US15439145

申请日：2017-02-22

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Mehul B. NAIK ,  Yong CAO ,  Mei-yee SHEK

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L23/53238 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber, wherein the substrate comprises a copper layer having an exposed surface and a low-k dielectric layer having an exposed surface, forming a metal layer over the exposed surface of the copper layer, wherein the exposed surface of the low-k dielectric layer is free from the metal layer, and forming a metal-based dielectric layer over the metal layer and over at least part of the exposed low-k dielectric surface, wherein the metal-based dielectric layer comprises an aluminum compound.

公开(公告)号：US20150221596A1

公开(公告)日：2015-08-06

申请号：US14173807

申请日：2014-02-05

Applicant: APPLIED MATERIALS, INC.

Inventor： He REN ,  Mehul B. NAIK ,  Yong CAO ,  Mei-Yee SHEK ,  Yana Cheng ,  Sree Rangasai V. Kesapragada

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber. The substrate has an exposed copper surface and an exposed low-k dielectric surface. A metal layer is formed over the copper surface but not over the low-k dielectric surface. A metal-based dielectric layer is formed over the metal layer and the low-k dielectric layer.

Abstract translation: 描述了用于半导体器件的互连结构及其制造方法。 该方法包括将基板定位在真空处理室中。 衬底具有暴露的铜表面和暴露的低k电介质表面。 在铜表面上形成金属层，但不在低k电介质表面上。 在金属层和低k电介质层上形成金属基介电层。

公开(公告)号：US20210123156A1

公开(公告)日：2021-04-29

申请号：US17016614

申请日：2020-09-10

Applicant: Applied Materials, Inc.

Inventor： Zihao YANG ,  Mingwei ZHU ,  Nag B. PATIBANDLA ,  Yong CAO ,  Shumao ZHANG ,  Zhebo CHEN ,  Jean LU ,  Daniel Lee DIEHL ,  Xianmin TANG

IPC: C30B23/00 ,  C30B29/40 ,  C30B33/04 ,  C23C14/06 ,  C23C14/34 ,  C23C14/54 ,  C23C14/58

Abstract: Embodiments described herein include a method for depositing a material layer on a substrate while controlling a bow of the substrate and a surface roughness of the material layer. A bias applied to the substrate while the material layer is deposited is adjusted to control the bow of the substrate. A bombardment process is performed on the material layer to improve the surface roughness of the material layer. The bias and bombardment process improve a uniformity of the material layer and reduce an occurrence of the material layer cracking due to the bow of the substrate.