A method of integrated circuit fabrication includes first forming at least one via in an insulting layer, and thereafter forming at least one trench-like structure separately. After a via is formed in an insulating layer, a layer of resist material is formed on the surface of the insulting layer and substantially filled the via. This step is followed by patterning at least one trench-like structure on the resist layer, and the trench-like structure is etched to the desired level. In some other embodiments, at least one trench-like structure is formed before at least one via is formed. An integrated circuit is manufactured by the aforementioned methods.