Invention Grant
- Patent Title: COL package having small chip hidden between leads
- Patent Title (中): 导线之间隐藏着小芯片的COL封装
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Application No.: US12719490Application Date: 2010-03-08
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Publication No.: US08125063B2Publication Date: 2012-02-28
- Inventor: Chin-Fa Wang
- Applicant: Chin-Fa Wang
- Applicant Address: TW Hsinchu
- Assignee: Powertech Technology, Inc.
- Current Assignee: Powertech Technology, Inc.
- Current Assignee Address: TW Hsinchu
- Agency: Muncy, Geissler, Olds & Lowe, PLLC
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L23/48

Abstract:
A Chip-On-Lead (COL) type semiconductor package having small chip hidden between leads is revealed. The lower surfaces of the leadframe's leads are attached to a wiring substrate and the leads are horizontally bent to form a die-holding cavity. A smaller chip is disposed on the wiring substrate by passing through the die-holding cavity to be on the same disposing level with the leads. At least a larger chip is disposed on the leads to overlap the smaller chip so that the small chip does not extrude from the leads. The encapsulant encapsulates a plurality of internal parts of the leads, the wiring substrate, and the larger chip. Therefore, the conventional unbalance issue of mold flow above and below the leads leading to cause excessive warpage can be avoided and numbers of stacked larger chips can be increased to have larger memory capacities.
Public/Granted literature
- US20110215454A1 COL PACKAGE HAVING SMALL CHIP HIDDEN BETWEEN LEADS Public/Granted day:2011-09-08
Information query
IPC分类: