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    Chip mounting device and chip package array
    2.
    发明申请
    Chip mounting device and chip package array 审中-公开
    芯片安装器件和芯片封装阵列

    公开(公告)号：US20090261463A1

    公开(公告)日：2009-10-22

    申请号：US12155350

    申请日：2008-06-03

    Applicant: Chin-Ti Chen ,  Chin-Fa Wang

    Inventor： Chin-Ti Chen ,  Chin-Fa Wang

    IPC: H01L23/495

    CPC classification number: H01L23/49565 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A chip mounting device includes at least one chip mounting unit and at least one side rail configured beside the chip mounting unit. The chip mounting unit includes a die pad and a plurality of conductive contacts. The side rail includes at least one identifying element. A chip package array with the above-mentioned chip mounting device is also disclosed. The chip mounting device and chip package array includes the identifying element configured on the side rail to improve the identification of semi-finished packaged chips during chip package process to be read automatically by machines instead of operators, and further decrease the loss caused by misjudgments of operators.

    Abstract translation: 芯片安装装置包括至少一个芯片安装单元和配置在芯片安装单元旁边的至少一个侧轨。 芯片安装单元包括芯片焊盘和多个导电触点。 侧轨包括至少一个识别元件。 还公开了具有上述芯片安装装置的芯片封装阵列。 芯片安装器件和芯片封装阵列包括配置在侧轨上的识别元件，以在芯片封装过程中改进半成品封装芯片的识别，以由机器而不是操作者自动读取，并进一步减少由错误判断引起的损失 运营商。

    COL package having small chip hidden between leads
    4.
    发明授权
    COL package having small chip hidden between leads 有权
    导线之间隐藏着小芯片的COL封装

    公开(公告)号：US08125063B2

    公开(公告)日：2012-02-28

    申请号：US12719490

    申请日：2010-03-08

    Applicant: Chin-Fa Wang

    Inventor： Chin-Fa Wang

    IPC: H01L23/495 ,  H01L23/48

    CPC classification number: H01L23/495 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: A Chip-On-Lead (COL) type semiconductor package having small chip hidden between leads is revealed. The lower surfaces of the leadframe's leads are attached to a wiring substrate and the leads are horizontally bent to form a die-holding cavity. A smaller chip is disposed on the wiring substrate by passing through the die-holding cavity to be on the same disposing level with the leads. At least a larger chip is disposed on the leads to overlap the smaller chip so that the small chip does not extrude from the leads. The encapsulant encapsulates a plurality of internal parts of the leads, the wiring substrate, and the larger chip. Therefore, the conventional unbalance issue of mold flow above and below the leads leading to cause excessive warpage can be avoided and numbers of stacked larger chips can be increased to have larger memory capacities.

    Abstract translation: 揭示了在引线之间隐藏有小芯片的芯片上导联（COL）型半导体封装。 引线框架的引线的下表面附接到布线基板，并且引线被水平弯曲以形成模具保持腔。 通过使模具保持腔通过与引线相同的配置水平，在布线基板上配置较小的芯片。 至少一个较大的芯片设置在引线上以与较小芯片重叠，使得小芯片不会从引线挤出。 密封剂封装引线，布线基板和较大芯片的多个内部部分。 因此，可以避免导致上下导线的模具流动的不均衡问题，导致过度翘曲，并且可以增加堆叠的较大芯片的数量以具有更大的存储容量。

    LEADFRAME-BASED SEMICONDUCTOR PACKAGE HAVING ARCHED BEND IN A SUPPORTING BAR AND LEADFRAME FOR THE PACKAGE
    5.
    发明申请
    LEADFRAME-BASED SEMICONDUCTOR PACKAGE HAVING ARCHED BEND IN A SUPPORTING BAR AND LEADFRAME FOR THE PACKAGE 有权
    基于LEADFRAME的半导体封装在支撑条和包装中的引线弯曲

    公开(公告)号：US20090302443A1

    公开(公告)日：2009-12-10

    申请号：US12133898

    申请日：2008-06-05

    Applicant: Chin-Fa Wang ,  Wan-Jung Hsieh ,  Yu-Mei Hsu

    Inventor： Chin-Fa Wang ,  Wan-Jung Hsieh ,  Yu-Mei Hsu

    IPC: H01L23/495

    CPC classification number: H01L23/4951 ,  H01L23/3107 ,  H01L23/49551 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A leadframe-based semiconductor package and a leadframe for the package are revealed. The semiconductor package primarily includes parts of the leadframe including one or more first leads, one or more second leads, and a supporting bar disposed between the first leads and the second leads and further includes a chip attached to the first leads, the second leads and the supporting bar, a plurality of bonding wires and an encapsulant. The supporting bar has an extended portion projecting from the first bonding finger and the second bonding finger and connected to a non-lead side of the encapsulant wherein the extended portion has an arched bend to absorb the pulling stresses and to block stress transmission. Cracks caused by delamination of the supporting bar will not be created during trimming the supporting bar along the non-lead side of the encapsulant. Moisture penetration along the cracks of the supporting bar to the die- bonding plane under the chip is desirably prevented.

    Abstract translation: 揭示了一种基于引线框架的半导体封装和封装的引线框架。 半导体封装主要包括引线框架的包括一个或多个第一引线，一个或多个第二引线和布置在第一引线和第二引线之间的支撑杆的部分，还包括附接到第一引线，第二引线和 支撑杆，多根接合线和密封剂。 支撑杆具有从第一接合指和第二接合指突起的延伸部分，并且连接到密封剂的非引线侧，其中延伸部具有拱形弯曲部以吸收拉应力并阻止应力传递。 在沿着密封剂的非引线侧修整支撑杆时不会产生由支撑杆分层引起的裂纹。 希望防止沿着支撑杆的裂纹向芯片下方的芯片接合平面的水分渗透。

    COL PACKAGE HAVING SMALL CHIP HIDDEN BETWEEN LEADS
    6.
    发明申请
    COL PACKAGE HAVING SMALL CHIP HIDDEN BETWEEN LEADS 有权
    COL包装在领先的小芯片之间隐藏

    公开(公告)号：US20110215454A1

    公开(公告)日：2011-09-08

    申请号：US12719490

    申请日：2010-03-08

    Applicant: Chin-Fa Wang

    Inventor： Chin-Fa Wang

    IPC: H01L23/495

    CPC classification number: H01L23/495 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: A Chip-On-Lead (COL) type semiconductor package having small chip hidden between leads is revealed. The lower surfaces of the leadframe's leads are attached to a wiring substrate and the leads are horizontally bent to form a die-holding cavity. A smaller chip is disposed on the wiring substrate by passing through the die-holding cavity to be on the same disposing level with the leads. At least a larger chip is disposed on the leads to overlap the smaller chip so that the small chip does not extrude from the leads. The encapsulant encapsulates a plurality of internal parts of the leads, the wiring substrate, and the larger chip. Therefore, the conventional unbalance issue of mold flow above and below the leads leading to cause excessive warpage can be avoided and numbers of stacked larger chips can be increased to have larger memory capacities.

    Abstract translation: 揭示了在引线之间隐藏有小芯片的芯片上导联（COL）型半导体封装。 引线框架的引线的下表面附接到布线基板，并且引线被水平弯曲以形成模具保持腔。 通过使模具保持腔通过与引线相同的配置水平，在布线基板上配置较小的芯片。 至少一个较大的芯片设置在引线上以与较小芯片重叠，使得小芯片不会从引线挤出。 密封剂封装引线，布线基板和较大芯片的多个内部部分。 因此，可以避免导致上下导线的模具流动的不均衡问题，导致过度翘曲，并且可以增加堆叠的较大芯片的数量以具有更大的存储容量。

    Leadframe and semiconductor package having downset baffle paddles
    10.
    发明授权
    Leadframe and semiconductor package having downset baffle paddles 有权
    引线框和半导体封装具有降压挡板

    公开(公告)号：US07812430B2

    公开(公告)日：2010-10-12

    申请号：US12042125

    申请日：2008-03-04

    Applicant: Chin-Fa Wang ,  Wan-Jung Hsieh ,  Yu-Mei Hsu

    Inventor： Chin-Fa Wang ,  Wan-Jung Hsieh ,  Yu-Mei Hsu

    IPC: H01L23/495

    CPC classification number: H01L23/49541 ,  H01L23/4951 ,  H01L23/49551 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A lead frame with downset baffle paddles and a semiconductor package utilizing the same are revealed. The lead frame primarily comprises a plurality of leads formed on a first plane, a baffle paddle formed on a second plane in parallel, and an internal tie bar formed between the first plane and the second plane. The internal tie bar has at least two or more windings such as “S” shaped to flexibly connect the baffle paddle to an adjacent one of the leads. Therefore, the internal tie bar can reduce the shifting and twisting of the connected lead during the formation of the downset of the baffle paddle.

    Abstract translation: 揭示了具有降压挡板的引线架和利用其的半导体封装。 引线框架主要包括形成在第一平面上的多个引线，平行地形成在第二平面上的挡板和形成在第一平面和第二平面之间的内部连接杆。 内部连接杆具有至少两个或更多个绕组，例如“S”形，以将挡板板柔性地连接到相邻的引线之间。 因此，内部连接杆可以减少在挡板形成下降期间所连接的引线的移动和扭转。

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