Invention Grant
- Patent Title: Sealing structure for high-K metal gate
- Patent Title (中): 高K金属门密封结构
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Application No.: US12389535Application Date: 2009-02-20
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Publication No.: US08193586B2Publication Date: 2012-06-05
- Inventor: Chien-Hao Chen , Hao-Ming Lien , Ssu-Yi Li , Jun-Lin Yeh , Kang-Cheng Lin , Kuo-Tai Huang , Chii-Horng Li , Chien-Hau Fei , Wen-Chih Yang , Jin-Aun Ng , Chi Hsin Chang , Chun Ming Lin , Harry Chuang , Chien-Liang Chen
- Applicant: Chien-Hao Chen , Hao-Ming Lien , Ssu-Yi Li , Jun-Lin Yeh , Kang-Cheng Lin , Kuo-Tai Huang , Chii-Horng Li , Chien-Hau Fei , Wen-Chih Yang , Jin-Aun Ng , Chi Hsin Chang , Chun Ming Lin , Harry Chuang , Chien-Liang Chen
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/8238

Abstract:
The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
Public/Granted literature
- US20100044803A1 SEALING STRUCTURE FOR HIGH-K METAL GATE AND METHOD OF MAKING Public/Granted day:2010-02-25
Information query
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