Invention Grant
US08913336B2 Constrained on-the-fly interleaver address generator circuits, systems, and methods
有权
约束的即时交织器地址发生器电路，系统和方法
- Patent Title: Constrained on-the-fly interleaver address generator circuits, systems, and methods
- Patent Title (中): 约束的即时交织器地址发生器电路，系统和方法
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Application No.: US14146032Application Date: 2014-01-02
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Publication No.: US08913336B2Publication Date: 2014-12-16
- Inventor: Sivagnanam Parthasarathy , Shayan Srinivasa Garani , Sudha Thipparthi
- Applicant: STMicroelectronics, Inc.
- Applicant Address: US TX Coppell
- Assignee: STMicroelectronics, Inc.
- Current Assignee: STMicroelectronics, Inc.
- Current Assignee Address: US TX Coppell
- Agency: Seed IP Law Group PLLC
- Main IPC: G11B5/09
- IPC: G11B5/09 ; G11B20/18 ; G11B27/30
Abstract:
An interleave address generation circuit includes a plurality of linear feedback shift registers operable to generate addresses for permuting a data block in a first domain to a data block in a second domain on a subword basis. The interleave address generation circuit is operable to generate the lane addresses for each subword and the linear feedback registers configured to generate circulant addresses and sub-circulant address to map bits in each subword in the data block in the first domain to a corresponding subword in the second domain.
Public/Granted literature
- US20140111882A1 CONSTRAINED ON-THE-FLY INTERLEAVER ADDRESS GENERATOR CIRCUITS, SYSTEMS, AND METHODS Public/Granted day:2014-04-24
Information query
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