公开(公告)号：US09837119B2

公开(公告)日：2017-12-05

申请号：US14949328

申请日：2015-11-23

Applicant: STMICROELECTRONICS, INC.

Inventor： Shayan Srinivasa Garani ,  Sivagnanam Parthasarathy

IPC: G11B27/36 ,  G11B20/18 ,  G06F11/20 ,  G11B20/10

CPC classification number: G11B20/1833 ,  G06F11/2094 ,  G06F2201/805 ,  G06F2201/85 ,  G11B20/10037 ,  G11B20/10046 ,  G11B20/10064 ,  G11B20/10074 ,  G11B20/10222 ,  G11B20/10287 ,  G11B20/10296 ,  G11B20/10379 ,  G11B2020/1823 ,  G11B2020/1826 ,  G11B2020/185 ,  G11B2020/1863 ,  G11B2220/2516

Abstract: An embodiment of a data-read path includes a defect detector and a data-recovery circuit. The defect detector is operable to identify a defective region of a data-storage medium, and the data-recovery circuit is operable to recover data from the data-storage medium in response to the defect detector. For example, such an embodiment may allow identifying a defective region of a data-storage disk caused, e.g., by a scratch or contamination, and may allow recovering data that was written to the defective region.

公开(公告)号：US09450618B2

公开(公告)日：2016-09-20

申请号：US14192674

申请日：2014-02-27

Applicant: STMICROELECTRONICS INC.

Inventor： Sivagnanam Parthasarathy ,  Lun Bin Huang ,  Alessandro Risso

IPC: H03M13/00 ,  H03M13/41 ,  G06F11/10 ,  G11B20/18 ,  H03M13/39

CPC classification number: H03M13/4146 ,  G06F11/1076 ,  G11B20/18 ,  H03M13/3905 ,  H03M13/3927 ,  H03M13/4184 ,  H03M13/42 ,  H03M13/6343 ,  H03M13/6502 ,  H04L1/0054 ,  H04L1/0055

Abstract: A modified soft output Viterbi algorithm (SOVA) detector receives a sequence of soft information values and determines a best path and an alternate path for each soft information value and further determines, when the best and alternate paths lead to the same value for a given soft information value, whether there is a third path departing from the alternate path that leads to an opposite decision with respect to the best path for a given soft information value. The SOVA detector then considers this third path when updating the reliability of the best path. The modified SOVA detector achieves max-log-map equivalence effectively through the Fossorier approach and includes modified reliability metric units for the first N stages of the SOVA detector, where N is the memory depth of a given path, and includes conventional reliability metric units for the remaining stages of the detector.

Abstract translation: 修改的软输出维特比算法（SOVA）检测器接收软信息值序列，并为每个软信息值确定最佳路径和备用路径，并且进一步确定当给定软件的最佳和替代路径导致相同值时 信息值，是否存在离开替代路径的第三路径，其导致相对于给定软信息值的最佳路径的相反决定。 然后，SOVA检测器在更新最佳路径的可靠性时考虑第三条路径。 改进的SOVA检测器通过Fossorier方法有效地实现了最大对数映射的等效性，并且包括SOVA检测器的前N个级的修正的可靠性度量单位，其中N是给定路径的存储器深度，并且包括用于 检测器的剩余阶段。

公开(公告)号：US08913336B2

公开(公告)日：2014-12-16

申请号：US14146032

申请日：2014-01-02

Applicant: STMicroelectronics, Inc.

Inventor： Sivagnanam Parthasarathy ,  Shayan Srinivasa Garani ,  Sudha Thipparthi

IPC: G11B5/09 ,  G11B20/18 ,  G11B27/30

CPC classification number: G11B27/3027 ,  G11B20/1833 ,  G11B20/1866 ,  G11B2020/185 ,  G11B2220/2516

Abstract: An interleave address generation circuit includes a plurality of linear feedback shift registers operable to generate addresses for permuting a data block in a first domain to a data block in a second domain on a subword basis. The interleave address generation circuit is operable to generate the lane addresses for each subword and the linear feedback registers configured to generate circulant addresses and sub-circulant address to map bits in each subword in the data block in the first domain to a corresponding subword in the second domain.

Abstract translation: 交错地址产生电路包括多个线性反馈移位寄存器，可操作以产生用于将第一域中的数据块置换为子字的第二域中的数据块的地址。 交织地址产生电路可操作以产生每个子字的通道地址和被配置为产生循环地址和子循环地址的线性反馈寄存器，以将第一域中的数据块中的每个子字中的位映射到第一域中的相应子字 第二个域名