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1.发明授权Constrained on-the-fly interleaver address generator circuits, systems, and methods 有权约束的即时交织器地址发生器电路，系统和方法公开(公告)号：US08913336B2
公开(公告)日：2014-12-16
申请号：US14146032
申请日：2014-01-02
Applicant: STMicroelectronics, Inc.
Inventor： Sivagnanam Parthasarathy , Shayan Srinivasa Garani , Sudha Thipparthi
CPC classification number: G11B27/3027 , G11B20/1833 , G11B20/1866 , G11B2020/185 , G11B2220/2516
Abstract: An interleave address generation circuit includes a plurality of linear feedback shift registers operable to generate addresses for permuting a data block in a first domain to a data block in a second domain on a subword basis. The interleave address generation circuit is operable to generate the lane addresses for each subword and the linear feedback registers configured to generate circulant addresses and sub-circulant address to map bits in each subword in the data block in the first domain to a corresponding subword in the second domain.
Abstract translation: 交错地址产生电路包括多个线性反馈移位寄存器，可操作以产生用于将第一域中的数据块置换为子字的第二域中的数据块的地址。 交织地址产生电路可操作以产生每个子字的通道地址和被配置为产生循环地址和子循环地址的线性反馈寄存器，以将第一域中的数据块中的每个子字中的位映射到第一域中的相应子字 第二个域名
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