Invention Grant
US09229798B2 Error handling method, memory storage device and memory controlling circuit unit
有权
错误处理方法,存储器存储器和存储器控制电路单元
- Patent Title: Error handling method, memory storage device and memory controlling circuit unit
- Patent Title (中): 错误处理方法,存储器存储器和存储器控制电路单元
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Application No.: US14248346Application Date: 2014-04-09
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Publication No.: US09229798B2Publication Date: 2016-01-05
- Inventor: Horng-Sheng Yan
- Applicant: PHISON ELECTRONICS CORP.
- Applicant Address: TW Miaoli
- Assignee: PHISON ELECTRONICS CORP.
- Current Assignee: PHISON ELECTRONICS CORP.
- Current Assignee Address: TW Miaoli
- Agency: Jianq Chyun IP Office
- Priority: TW103100843 20140109
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/07

Abstract:
An error handling method, a memory storage device and a memory controlling circuit unit are provided. The method includes obtaining a finished event corresponding to a channel; determining whether the finished event is a failed event, if the finished event is the failed event; stopping an operation of the channel and performing a first update operation on a counting value corresponding to the channel; and if the finished event is not the failed event, keeping the counting value corresponding to the channel unchanged and processing the finished event. The step of the processing the finished event includes performing a second update operation on the counting value corresponding to the channel if the finished event is the failed event, and recovering the operation of the channel if the counting value matches a threshold criterion. Accordingly, it can improve the accessing performance.
Public/Granted literature
- US20150193291A1 ERROR HANDLING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT Public/Granted day:2015-07-09
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