Invention Grant
- Patent Title: Clocking for pipelined routing
- Patent Title (中): 时钟流水线路由
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Application No.: US14075802Application Date: 2013-11-08
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Publication No.: US09360884B2Publication Date: 2016-06-07
- Inventor: David Galloway , David Lewis , Ryan Fung , Valavan Manohararajah , Jeffrey Christopher Chromczak
- Applicant: Altera Corporation
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: G06F13/34
- IPC: G06F13/34 ; G06F1/10 ; G06F1/08

Abstract:
An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers.
Public/Granted literature
- US20150134870A1 CLOCKING FOR PIPELINED ROUTING Public/Granted day:2015-05-14
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