公开(公告)号：US20190287638A1

公开(公告)日：2019-09-19

申请号：US16432638

申请日：2019-06-05

Applicant: Altera Corporation

Inventor： Ryan Fung ,  Valavan Manohararajah

IPC: G11C29/02 ,  G11C29/50 ,  H03K5/131 ,  H03K19/177

Abstract: Integrated circuits with memory interface circuitry may be provided. Prior to calibration, a number of samples may be determined by computing probability density function curves as a function of timing window edge asymmetry for different degrees of oversampling. During calibration, duty cycle distortion in data strobe signals may be corrected by selectively delaying the data strobe rising or falling edges. A data clock signal that is used for generating data signals may also suffer from duty cycle distortion. The rising and falling edges of the data clock signal may be selectively delayed to correct for duty cycle distortion. The data path through which the data signals are routed may be adjusted to equalize rising and falling transitions to minimize data path duty cycle distortion. Multi-rank calibration may be performed by calibrating to an intersection of successful settings that allow each memory rank to pass memory operation tests.

公开(公告)号：US20160239043A1

公开(公告)日：2016-08-18

申请号：US15141201

申请日：2016-04-28

Applicant: Altera Corporation

Inventor： David Galloway ,  David Lewis ,  Ryan Fung ,  Valavan Manohararajah ,  Jeffrey Christopher Chromczak

IPC: G06F1/10 ,  G06F13/40

CPC classification number: G06F1/10 ,  G06F1/08 ,  G06F13/4068

Abstract: An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers.

公开(公告)号：US09030231B1

公开(公告)日：2015-05-12

申请号：US14455014

申请日：2014-08-08

Applicant: Altera Corporation

Inventor： David Lewis ,  Valavan Manohararajah ,  David Galloway

IPC: H01L25/00 ,  H03K19/00 ,  G06F17/50 ,  H03K19/177

CPC classification number: H03K19/177 ,  G06F17/5054 ,  H01L25/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of configuring a programmable integrated circuit device with a user logic design includes analyzing the user logic design to identify unidirectional logic paths within the user logic design and cyclic logic paths within the user logic design, assigning the cyclic logic paths to logic in a first portion of the programmable integrated circuit device that operates at a first data rate, assigning the unidirectional logic paths to logic in a second portion of the programmable integrated circuit device that operates at a second data rate lower than the first data rate, and pipelining the unidirectional data paths in the second portion of the programmable integrated circuit device to compensate for the lower second data rate. A programmable integrated circuit device adapted to carry out such method may have logic regions operating at different rates, including logic regions with programmably selectable data rates.

Abstract translation: 配置具有用户逻辑设计的可编程集成电路设备的方法包括分析用户逻辑设计以识别用户逻辑设计内的用户逻辑设计中的单向逻辑路径和在用户逻辑设计内的循环逻辑路径，将循环逻辑路径分配给第一 可编程集成电路器件以第一数据速率工作的部分，将单向逻辑路径分配给可编程集成电路器件的第二部分中的逻辑，该第二部分以低于第一数据速率的第二数据速率工作;以及流水线化单向 可编程集成电路器件的第二部分中的数据路径，以补偿较低的第二数据速率。 适于执行这种方法的可编程集成电路设备可以具有以不同速率操作的逻辑区域，包括具有可编程选择的数据速率的逻辑区域。

公开(公告)号：US10832787B2

公开(公告)日：2020-11-10

申请号：US16432638

申请日：2019-06-05

Applicant: Altera Corporation

Inventor： Ryan Fung ,  Valavan Manohararajah

IPC: G11C7/00 ,  G11C29/02 ,  H03K5/131 ,  H03K19/17736 ,  G11C29/50

Abstract: Integrated circuits with memory interface circuitry may be provided. Prior to calibration, a number of samples may be determined by computing probability density function curves as a function of timing window edge asymmetry for different degrees of oversampling. During calibration, duty cycle distortion in data strobe signals may be corrected by selectively delaying the data strobe rising or falling edges. A data clock signal that is used for generating data signals may also suffer from duty cycle distortion. The rising and falling edges of the data clock signal may be selectively delayed to correct for duty cycle distortion. The data path through which the data signals are routed may be adjusted to equalize rising and falling transitions to minimize data path duty cycle distortion. Multi-rank calibration may be performed by calibrating to an intersection of successful settings that allow each memory rank to pass memory operation tests.

公开(公告)号：US10572224B2

公开(公告)日：2020-02-25

申请号：US15988458

申请日：2018-05-24

Applicant: Altera Corporation

Inventor： Valavan Manohararajah

IPC: G06F7/544

Abstract: An integrated circuit may have specialized processing blocks that are configurable to operate as arithmetic operators that may implement, amongst other functions, multiplication and multiply-accumulation operations in a first mode. In a second mode, a sequencer circuit may provide data signals and control signals to the specialized processing blocks such that the specialized processing block operates as a signal processing device that handles signals in a given sequence. For example, the sequencer circuit may control the signal arrival at the specialized processing block and the configuration of the configurable circuitry in the specialized processing block. In certain embodiments, the sequencer circuit and the specialized processing block may implement finite impulse response (FIR) filters.

公开(公告)号：US10452392B1

公开(公告)日：2019-10-22

申请号：US14600322

申请日：2015-01-20

Applicant: Altera Corporation

Inventor： David Lewis ,  Valavan Manohararajah

IPC: G06F9/30

Abstract: A programmable integrated circuit device includes a plurality of clusters of programmable logic resources. Programmable device interconnect resources allow user-defined interconnection between the clusters of programmable logic resources. A plurality of specialized processing blocks have dedicated arithmetic operators and programmable internal interconnect resources, and having inputs and outputs programmably connectable to the programmable device interconnect resources. A plurality of embedded memory modules have inputs and outputs programmably connectable to the programmable device interconnect resources. Instruction sequencing circuitry is provided, and the instruction sequencing circuitry, at least one of the specialized processing blocks and at least one of the embedded memory modules, are programmably connectable to form a processor, where the memory module serves as instruction memory. Optionally, a dedicated instruction bus communicates the instructions from the embedded memory module or modules to the specialized processing block or blocks.

公开(公告)号：US09660650B1

公开(公告)日：2017-05-23

申请号：US14209503

申请日：2014-03-13

Applicant: Altera Corporation

Inventor： Valavan Manohararajah ,  Jeffrey Christopher Chromczak ,  David Lewis

IPC: H03K19/173 ,  H03K19/0175 ,  G06F17/50

CPC classification number: H03K19/017581 ,  G06F17/505 ,  H03K19/17728 ,  H03K19/17744

Abstract: Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions include register circuitry that may be controlled by register control signals. A clock enable feedback loop circuit controlled by a clock enable control signal may couple the register output to the register input. The clock enable feedback loop circuit may facilitate adjustment of register locations within a design while ensuring correct clock enable functionality. A group of programmable logic regions may have shared input selection circuitry that selects register control signals and produces delayed versions of the signals that are shared by the group. If desired, each programmable logic region may be provided with adjustable delay circuitry that individually adjusts control signal delay for registers of that programmable logic region.

公开(公告)号：US09589090B1

公开(公告)日：2017-03-07

申请号：US14466610

申请日：2014-08-22

Applicant: Altera Corporation

Inventor： Deshanand Singh ,  Valavan Manohararajah ,  Gordon Raymond Chiu ,  Ivan Blunno ,  Stephen D. Brown

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/505 ,  G06F17/5077

Abstract: A method for designing a system on a target device includes entering the system. The system is synthesized. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system immediately after more than one of the entering, synthesizing, mapping, placing and routing procedures.

Abstract translation: 用于在目标设备上设计系统的方法包括进入系统。 系统合成。 系统映射。 系统放在目标设备上。 系统被路由。 在多个进入，合成，映射，放置和布线过程之后，立即在系统上进行物理合成。

公开(公告)号：US09558849B1

公开(公告)日：2017-01-31

申请号：US14060920

申请日：2013-10-23

Applicant: Altera Corporation

Inventor： Ryan Fung ,  Valavan Manohararajah

IPC: G11C7/00 ,  G11C29/50

CPC classification number: G11C29/022 ,  G11C29/023 ,  G11C29/50012 ,  H03K5/131 ,  H03K19/17744

Abstract: Integrated circuits with memory interface circuitry may be provided. Prior to calibration, a number of samples may be determined by computing probability density function curves as a function of timing window edge asymmetry for different degrees of oversampling. During calibration, duty cycle distortion in data strobe signals may be corrected by selectively delaying the data strobe rising or falling edges. A data clock signal that is used for generating data signals may also suffer from duty cycle distortion. The rising and falling edges of the data clock signal may be selectively delayed to correct for duty cycle distortion. The data path through which the data signals are routed may be adjusted to equalize rising and falling transitions to minimize data path duty cycle distortion. Multi-rank calibration may be performed by calibrating to an intersection of successful settings that allow each memory rank to pass memory operation tests.

Abstract translation: 可以提供具有存储器接口电路的集成电路。 在校准之前，可以通过计算不同程度的过采样的时间窗口边缘不对称的函数的概率密度函数曲线来确定多个样本。 在校准期间，可以通过选择性地延迟数据选通上升沿或下降沿来校正数据选通信号中的占空比失真。 用于产生数据信号的数据时钟信号也可能遭受占空比失真。 可以选择性地延迟数据时钟信号的上升沿和下降沿以校正占空比失真。 可以调整数据信号路由的数据路径以均衡上升和下降转换，以最小化数据路径占空比失真。 可以通过校准到允许每个存储器等级通过存储器操作测试的成功设置的交集来执行多级校准。

公开(公告)号：US09360884B2

公开(公告)日：2016-06-07

申请号：US14075802

申请日：2013-11-08

Applicant: Altera Corporation

Inventor： David Galloway ,  David Lewis ,  Ryan Fung ,  Valavan Manohararajah ,  Jeffrey Christopher Chromczak

IPC: G06F13/34 ,  G06F1/10 ,  G06F1/08

CPC classification number: G06F1/10 ,  G06F1/08 ,  G06F13/4068

Abstract: An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers.

Abstract translation: 集成电路可以具有流水线可编程互连，其被配置为在存储在寄存器中的路由信号与绕过寄存器的相同路由信号之间进行选择。 流水线可编程互连可以通过线将所选择的路由信号发送到下一个流水线可编程互连电路。 集成电路还可以具有时钟路由选择电路，以选择用于不同流水线可编程互连中的寄存器的相应时钟信号。 时钟路由电路可以包括传送区域时钟的第一互连，传送路由时钟的第二互连，第一选择器电路，以选择区域时钟之间的路由时钟;以及第二选择器电路，以选择各个寄存器的路由时钟。