公开(公告)号：US20200257839A1

公开(公告)日：2020-08-13

申请号：US16859732

申请日：2020-04-27

Applicant: Altera Corporation

Inventor： Junaid Asim Khan ,  Gabriel Quan ,  Ketan Padalia ,  Scott James Brissenden ,  Ryan Fung

IPC: G06F30/327 ,  G06F30/392 ,  G06F30/394

Abstract: A method for implementing physical optimizations includes performing physical optimizations on a first reference version of a design, maintaining a computer-readable list of the physical optimizations, and during a subsequent compile for a second version of the design: identifying matching cells, nets, or both between the first reference version of the design and the second version of the design; and restoring at least a subset of the physical optimizations in the second version of the design by reading the computer-readable list of the physical optimizations and applying the subset to a computer-readable description of the second version of the design.

公开(公告)号：US20190287638A1

公开(公告)日：2019-09-19

申请号：US16432638

申请日：2019-06-05

Applicant: Altera Corporation

Inventor： Ryan Fung ,  Valavan Manohararajah

IPC: G11C29/02 ,  G11C29/50 ,  H03K5/131 ,  H03K19/177

Abstract: Integrated circuits with memory interface circuitry may be provided. Prior to calibration, a number of samples may be determined by computing probability density function curves as a function of timing window edge asymmetry for different degrees of oversampling. During calibration, duty cycle distortion in data strobe signals may be corrected by selectively delaying the data strobe rising or falling edges. A data clock signal that is used for generating data signals may also suffer from duty cycle distortion. The rising and falling edges of the data clock signal may be selectively delayed to correct for duty cycle distortion. The data path through which the data signals are routed may be adjusted to equalize rising and falling transitions to minimize data path duty cycle distortion. Multi-rank calibration may be performed by calibrating to an intersection of successful settings that allow each memory rank to pass memory operation tests.

公开(公告)号：US20160239043A1

公开(公告)日：2016-08-18

申请号：US15141201

申请日：2016-04-28

Applicant: Altera Corporation

Inventor： David Galloway ,  David Lewis ,  Ryan Fung ,  Valavan Manohararajah ,  Jeffrey Christopher Chromczak

IPC: G06F1/10 ,  G06F13/40

CPC classification number: G06F1/10 ,  G06F1/08 ,  G06F13/4068

Abstract: An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers.

公开(公告)号：US20210082534A1

公开(公告)日：2021-03-18

申请号：US17093292

申请日：2020-11-09

Applicant: Altera Corporation

Inventor： Ryan Fung ,  Valavan Manohararajah

IPC: G11C29/02 ,  H03K5/131 ,  H03K19/17736 ,  G11C29/50

Abstract: Integrated circuits with memory interface circuitry may be provided. Prior to calibration, a number of samples may be determined by computing probability density function curves as a function of timing window edge asymmetry for different degrees of oversampling. During calibration, duty cycle distortion in data strobe signals may be corrected by selectively delaying the data strobe rising or falling edges. A data clock signal that is used for generating data signals may also suffer from duty cycle distortion. The rising and falling edges of the data clock signal may be selectively delayed to correct for duty cycle distortion. The data path through which the data signals are routed may be adjusted to equalize rising and falling transitions to minimize data path duty cycle distortion. Multi-rank calibration may be performed by calibrating to an intersection of successful settings that allow each memory rank to pass memory operation tests.

公开(公告)号：US10096349B2

公开(公告)日：2018-10-09

申请号：US15156186

申请日：2016-05-16

Applicant: Altera Corporation

Inventor： Ryan Fung ,  Joshua David Fender

IPC: G11C7/22 ,  G11C7/10

Abstract: An apparatus includes an interface circuit coupled to an electronic device. The interface circuit provides source synchronous communication with the electronic device using a strobe signal. The interface circuit is configured to gate the strobe signal in order to successfully communicate with the electronic device.

公开(公告)号：US20180151243A1

公开(公告)日：2018-05-31

申请号：US15878284

申请日：2018-01-23

Applicant: Altera Corporation

Inventor： Ryan Fung ,  Valavan Manohararajah

IPC: G11C29/02

CPC classification number: G11C29/022 ,  G11C29/023 ,  G11C29/50012 ,  H03K5/131 ,  H03K19/17744

Abstract: Integrated circuits with memory interface circuitry may be provided. Prior to calibration, a number of samples may be determined by computing probability density function curves as a function of timing window edge asymmetry for different degrees of oversampling. During calibration, duty cycle distortion in data strobe signals may be corrected by selectively delaying the data strobe rising or falling edges. A data clock signal that is used for generating data signals may also suffer from duty cycle distortion. The rising and falling edges of the data clock signal may be selectively delayed to correct for duty cycle distortion. The data path through which the data signals are routed may be adjusted to equalize rising and falling transitions to minimize data path duty cycle distortion. Multi-rank calibration may be performed by calibrating to an intersection of successful settings that allow each memory rank to pass memory operation tests.

公开(公告)号：US09245085B2

公开(公告)日：2016-01-26

申请号：US14484655

申请日：2014-09-12

Applicant: Altera Corporation

Inventor： Ryan Fung ,  David Lewis ,  Valavan Manohararajah

IPC: G06F17/50 ,  H03K19/177

CPC classification number: G06F17/5054 ,  G06F17/50 ,  G06F17/5045 ,  G06F17/5059 ,  G06F17/5077 ,  G06F2217/84 ,  H03K19/17728 ,  H03K19/17736

Abstract: A method of configuring an integrated circuit device with a user logic design includes analyzing the user logic design to identify timing requirements of paths within the user logic design, determining latency requirements along those paths, routing the user logic design based on availability of storage elements for incorporation into those paths to satisfy the latency requirements, and retiming the user logic design following that routing by incorporating at least some of the storage elements.

Abstract translation: 配置具有用户逻辑设计的集成电路设备的方法包括分析用户逻辑设计以识别用户逻辑设计内的路径的定时要求，确定沿着这些路径的等待时间要求，基于存储元件的可用性路由用户逻辑设计， 并入到这些路径中以满足等待时间要求，并且通过并入至少一些存储元件来重新定时跟踪该路由之后的用户逻辑设计。

公开(公告)号：US09166570B2

公开(公告)日：2015-10-20

申请号：US13964901

申请日：2013-08-12

Applicant: Altera Corporation

Inventor： David Lewis ,  Jeffrey Christopher Chromczak ,  Ryan Fung

IPC: H03K19/00 ,  H03K3/356 ,  H03K3/037 ,  H03K19/003 ,  H03K19/177

CPC classification number: H03K3/356008 ,  H03K3/0375 ,  H03K19/00315 ,  H03K19/17764

Abstract: An integrated circuit (IC) includes a set of metastability-hardened storage circuits. Each metastability-hardened storage circuit may include: (a) a pulse width distortion circuit; (b) a first circuit powered by a nominal power supply voltage, and a second circuit powered by a higher-than-nominal supply voltage; (c) an inverter and a bias circuit, where the bias circuit provides a bias current based on an intermediate state of the inverter to resolve a metastable state of the inverter; or (d) a latch, and a dynamic bias circuit that causes current to be injected into the latch to resolve a metastable state of the latch.

Abstract translation: 集成电路（IC）包括一组亚稳态硬化存储电路。 每个亚硬化存储电路可以包括：（a）脉冲宽度失真电路; （b）由标称电源电压供电的第一电路和由高于标称电源电压供电的第二电路; （c）逆变器和偏置电路，其中所述偏置电路基于所述逆变器的中间状态提供偏置电流以解决所述逆变器的亚稳态; 或（d）锁存器和动态偏置电路，其使电流注入到锁存器中以解决闩锁的亚稳态。

公开(公告)号：US20150134870A1

公开(公告)日：2015-05-14

申请号：US14075802

申请日：2013-11-08

Applicant: Altera Corporation

Inventor： David Galloway ,  David Lewis ,  Ryan Fung ,  Valavan Manohararajah ,  Jeffrey Christopher Chromczak

IPC: G06F1/10

CPC classification number: G06F1/10 ,  G06F1/08 ,  G06F13/4068

Abstract: An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers.

Abstract translation: 集成电路可以具有流水线可编程互连，其被配置为在存储在寄存器中的路由信号与绕过寄存器的相同路由信号之间进行选择。 流水线可编程互连可以通过线将所选择的路由信号发送到下一个流水线可编程互连电路。 集成电路还可以具有时钟路由选择电路，以选择用于不同流水线可编程互连中的寄存器的相应时钟信号。 时钟路由电路可以包括传送区域时钟的第一互连，传送路由时钟的第二互连，第一选择器电路，以选择区域时钟之间的路由时钟;以及第二选择器电路，以选择各个寄存器的路由时钟。

公开(公告)号：US09024683B1

公开(公告)日：2015-05-05

申请号：US14022931

申请日：2013-09-10

Applicant: Altera Corporation

Inventor： David Lewis ,  Ryan Fung

IPC: H03K5/00

CPC classification number: H03K5/00 ,  G06F1/10 ,  G06F1/26 ,  H03K19/00346

Abstract: A clock network includes a first plurality of shield wires associated with a first plurality of clock lines and a second plurality of shield wires associated with a second plurality of clock lines. The clock network also includes a first plurality of clock activity program circuits associated with the first plurality of clock lines and a second plurality of clock activity program circuits associated with the second plurality of clock lines, wherein the first and second plurality of shield wires and the first and second plurality clock activity program circuits are configured to reduce power spikes.

Abstract translation: 时钟网络包括与第一多个时钟线相关联的第一多个屏蔽线和与第二多个时钟线相关联的第二多个屏蔽线。 时钟网络还包括与第一多个时钟线相关联的第一多个时钟活动程序电路和与第二多个时钟线相关联的第二多个时钟活动程序电路，其中第一和第二多个屏蔽线和 第一和第二多个时钟活动程序电路被配置为减少功率尖峰。