Invention Grant
- Patent Title: Operating method of NAND flash memory unit
- Patent Title (中): NAND闪存单元的操作方法
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Application No.: US14943035Application Date: 2015-11-17
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Publication No.: US09437309B2Publication Date: 2016-09-06
- Inventor: Wei Lin , Yu-Cheng Hsu , Kuo-Yi Cheng
- Applicant: PHISON ELECTRONICS CORP.
- Applicant Address: TW Miaoli
- Assignee: PHISON ELECTRONICS CORP.
- Current Assignee: PHISON ELECTRONICS CORP.
- Current Assignee Address: TW Miaoli
- Agency: Jianq Chyun IP Office
- Priority: TW102110527U 20130325
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C16/14 ; G11C16/26 ; H01L29/792 ; H01L27/115 ; G11C11/56 ; G11C16/04

Abstract:
A NAND flash memory unit, an operating method and a reading method are provided. The NAND flash memory unit includes a plurality of gate layers, a tunnel layer, a charge trapping layer, a conductor layer and a second dielectric layer. A first dielectric layer is included between two adjacent gate layers among the gate layers. The tunnel layer, the charge trapping layer, the conductor layer, and the second dielectric layer penetrate the gate layers. The charge trapping layer is disposed between the tunnel layer and the gate layers, and the second dielectric layer is disposed between the conductor layer and the tunnel layer. Therefore, an erasing speed may be increased; the charge trapping layer may be repaired; the controllability of the gate layers may be increased.
Public/Granted literature
- US20160078952A1 OPERATING METHOD OF NAND FLASH MEMORY UNIT Public/Granted day:2016-03-17
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