In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.