A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. A sampled loop filter (SLPF) in the phase locked loop may capture charge from a charge pump (CHP) in the phase locked loop and the charge is captured at a frequency corresponding to the frequency of the reference clock signal. A switch of the sampled loop filter is utilized and controlled to manage holding and releasing of the captured charge, where the switch is controlled utilizing a control signal. By utilizing the sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of the charge pump, disturbance which is associated with duty cycle errors of the crystal clock signal.