Invention Grant
- Patent Title: Sampling circuit with reduced metastability exposure
- Patent Title (中): 具有降低亚稳态暴露的采样电路
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Application No.: US14927964Application Date: 2015-10-30
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Publication No.: US09552892B1Publication Date: 2017-01-24
- Inventor: Stephen V. Kosonocky , Krishnan T. Sukumar
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Zagorin Cave LLP
- Main IPC: H03M1/00
- IPC: H03M1/00 ; G11C27/02 ; H03K17/687 ; H03K3/3562 ; H03K3/356
Abstract:
A sampling circuit uses an input stage to sample an input signal and a secondary evaluation stage to maintain the output state of the input stage. Once the input stage transitions at a clock transition, the secondary evaluation stage uses regenerative feedback devices to hold the state to help ensure the sampling circuit only switches once during an evaluation.
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