Invention Grant
US09577100B2 FinFET and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions
有权
具有悬浮沟道区域的FinFET和纳米线半导体器件以及围绕悬浮沟道区域的栅极结构
- Patent Title: FinFET and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions
- Patent Title (中): 具有悬浮沟道区域的FinFET和纳米线半导体器件以及围绕悬浮沟道区域的栅极结构
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Application No.: US14305543Application Date: 2014-06-16
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Publication No.: US09577100B2Publication Date: 2017-02-21
- Inventor: Kangguo Cheng , Michael P. Chudzik , Eric C. Harley , Judson R. Holt , Yue Ke , Rishikesh Krishnan , Kern Rim , Henry K. Utomo
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Hoffman Warnick LLC
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/78 ; H01L29/66 ; H01L29/161 ; H01L29/10 ; B82Y10/00 ; H01L29/423 ; H01L29/775 ; H01L29/06 ; H01L21/306 ; H01L29/165
Abstract:
A semiconductor device including at least one suspended channel structure of a silicon including material, and a gate structure present on the suspended channel structure. At least one gate dielectric layer is present surrounding the suspended channel structure, and at least one gate conductor is present on the at least one gate dielectric layer. Source and drain structures may be composed of a silicon and germanium including material. The source and drain structures are in contact with the source and drain region ends of the suspended channel structure through a silicon cladding layer.
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