Invention Grant
- Patent Title: Buffer memory management method, memory control circuit unit and memory storage device
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Application No.: US14930666Application Date: 2015-11-03
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Publication No.: US09639475B2Publication Date: 2017-05-02
- Inventor: Kok-Yong Tan
- Applicant: PHISON ELECTRONICS CORP.
- Applicant Address: JP Miaoli
- Assignee: PHISON ELECTRONICS CORP.
- Current Assignee: PHISON ELECTRONICS CORP.
- Current Assignee Address: JP Miaoli
- Agency: Jianq Chyun IP Office
- Priority: TW104131487A 20150923
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/1009 ; G06F12/02

Abstract:
A buffer memory management method, a memory control circuit unit and a memory storage device are provided. The buffer memory management method includes allocating a mapping table zone having a first zone and a second zone in the buffer memory, and temporarily storing a plurality of logical address-physical address mapping tables into the first zone and the second zone, and receiving a first write command which indicates writing first data into a first logical address. A first logical address-physical address mapping table to which the first logical address belongs is temporarily stored into a first buffer unit in the second zone. The method also includes updating the first logical address-physical address mapping table, moving the updated first logical address-physical address mapping table into a second buffer unit in the first zone, and marking the second buffer unit as a dirty status.
Public/Granted literature
- US20170083451A1 BUFFER MEMORY MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE Public/Granted day:2017-03-23
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