Invention Grant
- Patent Title: Integrated circuit chip reliability using reliability-optimized failure mechanism targeting
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Application No.: US14742801Application Date: 2015-06-18
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Publication No.: US09639645B2Publication Date: 2017-05-02
- Inventor: Jeanne P. Bickford , Nazmul Habib , Baozhen Li , Tad J. Wilder
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Gibb & Riley, LLC
- Agent David A. Cain, Esq.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Disclosed are methods for improving integrated circuit (IC) chip reliability. IC chips are manufactured and sorted into groups corresponding to process windows within a process distribution for the design. Group fail rates are set for each group based on failure mechanism fail rates, which are set for multiple failure mechanisms. An overall fail rate is determined for the full process distribution based on the group fail rates. First contribution amounts of the groups to the overall fail rate and second contribution amounts of the failure mechanisms to the group fail rate of each group are determined. Based on an analysis of the contribution amounts, at least one specific failure mechanism is selected and targeted for improvement (i.e., changes directed to the specific failure mechanism(s) are proposed and implemented). Optionally, proposed change(s) are only implemented if they will be sufficient to meet a reliability requirement and/or will not be cost-prohibitive.
Public/Granted literature
- US20160371413A1 INTEGRATED CIRCUIT CHIP RELIABILITY USING RELIABILITY-OPTIMIZED FAILURE MECHANISM TARGETING Public/Granted day:2016-12-22
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