Invention Grant
- Patent Title: Double plated conductive pillar package substrate
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Application No.: US14750880Application Date: 2015-06-25
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Publication No.: US09754906B2Publication Date: 2017-09-05
- Inventor: Li-Chuan Tsai , Chih-Cheng Lee
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaohsiung
- Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee Address: TW Kaohsiung
- Agency: Foley & Lardner LLP
- Agent Cliff Z. Liu
- Main IPC: H01L23/00
- IPC: H01L23/00
Abstract:
The present disclosure relates to a package substrate. The package substrate includes a patterned conductive layer and conductive pillars. Each of the conductive pillars includes a first portion and a second portion, where the first portion contacts the patterned conductive layer at one end of the first portion, and the second portion is adjacent to another end of the first portion. A thickness of the first portion is greater than a thickness of the second portion. Side surfaces of the first portion are substantially coplanar to side surfaces of the second portion.
Public/Granted literature
- US20160379950A1 DOUBLE PLATED CONDUCTIVE PILLAR PACKAGE SUBSATRATE Public/Granted day:2016-12-29
Information query
IPC分类:
