Invention Grant
- Patent Title: III-N material structure for gate-recessed transistors
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Application No.: US15389255Application Date: 2016-12-22
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Publication No.: US09755062B2Publication Date: 2017-09-05
- Inventor: Han Wui Then , Marko Radosavljevic , Uday Shah , Niloy Mukherjee , Ravi Pillarisetty , Benjamin Chu-Kung , Jack T. Kavalieros , Robert S. Chau
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- Main IPC: H01L21/268
- IPC: H01L21/268 ; H01L29/778 ; H01L29/20 ; H01L29/205 ; H01L29/40 ; H01L21/02 ; H01L21/306 ; H01L21/311 ; H01L29/423 ; H01L29/51 ; H01L29/66 ; H01L29/36

Abstract:
III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.
Public/Granted literature
- US20170104094A1 III-N MATERIAL STRUCTURE FOR GATE-RECESSED TRANSISTORS Public/Granted day:2017-04-13
Information query
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