Invention Grant
- Patent Title: Multi-layer packaging scheme for implant electronics
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Application No.: US14981432Application Date: 2015-12-28
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Publication No.: US09773715B2Publication Date: 2017-09-26
- Inventor: Yu-Chong Tai , Han-Chieh Chang
- Applicant: California Institute of Technology
- Applicant Address: US CA Pasadena
- Assignee: California Institute of Technology
- Current Assignee: California Institute of Technology
- Current Assignee Address: US CA Pasadena
- Agency: Kilpatrick Townsend & Stockton LLP
- Main IPC: H01L23/31
- IPC: H01L23/31 ; A61B50/30 ; B81C1/00 ; A61N1/375 ; A61F2/14 ; A61N1/36 ; H01L21/56 ; H01L23/00 ; A61N1/372

Abstract:
The present invention provides a micropackaged device comprising: a substrate for securing a device with a corrosion barrier affixed to the substrate, wherein the corrosion barrier comprises a first thin-film layer, a metal film coating the thin-film layer and a second thin-film layer to provide a sandwich layer; and optionally at least one feedthrough disposed in the substrate to permit at least one input and or at least one output line into the micropackaged device, wherein the micropackaged device is encapsulated by the corrosion barrier. Methods of producing the micropackaged device are also disclosed.
Public/Granted literature
- US20160133540A1 MULTI-LAYER PACKAGING SCHEME FOR IMPLANT ELECTRONICS Public/Granted day:2016-05-12
Information query
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