Invention Grant
- Patent Title: Method for fabricating transistor with thinned channel
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Application No.: US15069726Application Date: 2016-03-14
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Publication No.: US09806195B2Publication Date: 2017-10-31
- Inventor: Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/423 ; H01L29/66 ; H01L29/06 ; H01L29/08 ; H01L29/10 ; H01L29/161 ; H01L29/165 ; H01L29/24 ; H01L29/267 ; H01L29/49 ; H04B1/3827
Abstract:
A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
Public/Granted literature
- US20160197185A1 METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL Public/Granted day:2016-07-07
Information query
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