Invention Grant
- Patent Title: Low-power low density parity check decoding
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Application No.: US15358473Application Date: 2016-11-22
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Publication No.: US09838035B2Publication Date: 2017-12-05
- Inventor: Mingrui Zhu , Curtis Ling , Timothy Gallagher
- Applicant: MaxLinear, Inc.
- Applicant Address: US CA Carlsbad
- Assignee: MaxLinear, Inc.
- Current Assignee: MaxLinear, Inc.
- Current Assignee Address: US CA Carlsbad
- Agency: McAndrews, Held & Malloy
- Main IPC: H03M13/11
- IPC: H03M13/11 ; H03M13/00 ; H04L1/00

Abstract:
In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node.
Public/Granted literature
- US20170077953A1 Low-Power Low Density Parity Check Decoding Public/Granted day:2017-03-16
Information query
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