公开(公告)号：US10063399B2

公开(公告)日：2018-08-28

申请号：US14687234

申请日：2015-04-15

Applicant: MaxLinear, Inc.

Inventor： Mingrui Zhu ,  Arun Kedambadi ,  Seung Chul Hong ,  Anand Anandakumar

IPC: H04K1/10 ,  H04L27/28 ,  H04L27/26 ,  H04L25/02

Abstract: Methods and systems are provided for adaptive guard interval (GI) combining. When a signal carrying at least one symbol that is preceded by a guard interval that comprises a portion of the symbol is received, a portion of the guard interval that is free from inter-symbol interference (ISI) may be determined, and only a part of the ISI-free portion of the guard interval may be extracted. The part of the ISI-free portion of the guard interval may be selected based on timing adjustment, relative to start of the symbol, that is applied to a function used in extracting the symbol. The extracted part of the ISI-free portion of the guard interval may then be combined with a corresponding portion of the symbol. The extracting and/or combining may be performed after a determination that a delay spread is smaller than a predetermined channel delay.

公开(公告)号：US10425262B2

公开(公告)日：2019-09-24

申请号：US16113527

申请日：2018-08-27

Applicant: MaxLinear, Inc.

Inventor： Mingrui Zhu ,  Arun Kedambadi ,  Seung Chul Hong ,  Anand Anandakumar

IPC: H04L27/26 ,  H04L25/02

Abstract: Methods and systems are provided for adaptive guard interval (GI) combining. A signal carrying a symbol that is preceded by a guard interval (GI) that includes a portion of the symbol may be received, and a portion of the GI that is free from inter-symbol interference (ISI) may be determined. Only a part of the ISI-free portion of the GI may be selected. The selected part of the ISI-free portion of the GI may be less than a whole of the ISI-free portion. The selection may be configured based on a parameter that is applied to a function used in extracting the symbol. The parameter may be a timing adjustment, relative to a start of the symbol, applied to the function when extracting the symbol. Only the part of the ISI-free portion of the GI may then be extracted and combined with a corresponding portion of the symbol.

公开(公告)号：US10097193B2

公开(公告)日：2018-10-09

申请号：US15812365

申请日：2017-11-14

Applicant: Maxlinear, Inc.

Inventor： Pawandeep Taluja ,  Mingrui Zhu ,  Xuefeng Chen ,  Anand Anandakumar ,  Sheng Ye ,  Timothy Gallagher

IPC: H03M1/06 ,  H04W56/00 ,  H03M1/50 ,  H03M1/12 ,  H03M1/10

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

公开(公告)号：US20170163277A1

公开(公告)日：2017-06-08

申请号：US15436088

申请日：2017-02-17

Applicant: Maxlinear, Inc.

Inventor： Pawandeep Taluja ,  Mingrui Zhu ,  Xuefeng Chen ,  Anand Anandakumar ,  Sheng Ye ,  Timothy Leo Gallagher

IPC: H03M1/06 ,  H04W56/00 ,  H03M1/50 ,  H03M1/12 ,  H03M1/10

CPC classification number: H03M1/0612 ,  H03M1/1009 ,  H03M1/1038 ,  H03M1/1215 ,  H03M1/50 ,  H04L7/0087 ,  H04L25/08 ,  H04W56/00

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

公开(公告)号：US09577655B2

公开(公告)日：2017-02-21

申请号：US14920699

申请日：2015-10-22

Applicant: Maxlinear, Inc.

Inventor： Pawandeep Taluja ,  Mingrui Zhu ,  Xuefeng Chen ,  Anand Anandakumar ,  Sheng Ye ,  Timothy Leo Gallagher

IPC: H03M1/06 ,  H03M1/50 ,  H03M1/10 ,  H03M1/12 ,  H04L7/00 ,  H04L25/08 ,  H04W56/00

CPC classification number: H03M1/0612 ,  H03M1/1009 ,  H03M1/1038 ,  H03M1/1215 ,  H03M1/50 ,  H04L7/0087 ,  H04L25/08 ,  H04W56/00

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

Abstract translation: 用于时间交织的模数转换器定时失配校准和补偿的方法和系统可以包括在芯片上接收模拟信号，使用时间交织的模数转换器（ADC）将模拟信号转换成数字信号， 并且通过估计期望的数字输出信号和阻塞信号之间的复数耦合系数，将在时间交错ADC中的定时偏移上的混叠在期望信号上的阻塞信号减少。 解相关算法可以包括对称自适应去相关算法。 所接收的模拟信号可以由芯片上的校准音发生器产生。 混叠信号可以与来自乘法器的输出信号相加。 复数耦合系数可以利用求和信号上的去相关算法来确定。 乘法器可以被配置为利用所确定的复耦合系数来消除阻塞信号。

公开(公告)号：US20190044525A1

公开(公告)日：2019-02-07

申请号：US16154167

申请日：2018-10-08

Applicant: Maxlinear, Inc.

Inventor： Pawandeep Taluja ,  Mingrui Zhu ,  Xuefeng Chen ,  Anand Anandakumar ,  Sheng Ye ,  Timothy Gallagher

IPC: H03M1/06 ,  H04L7/00 ,  H04L25/08 ,  H03M1/10 ,  H03M1/50 ,  H04W56/00 ,  H03M1/12

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

公开(公告)号：US10069514B2

公开(公告)日：2018-09-04

申请号：US15832030

申请日：2017-12-05

Applicant: MaxLinear, Inc.

Inventor： Mingrui Zhu ,  Curtis Ling ,  Timothy Gallagher

IPC: H03M13/11 ,  H03M13/00 ,  H04L1/00

Abstract: Methods and systems are provided for low-power decoding. An example system may include one or more storage circuits and a decoder circuit. The decoder circuit may implement a plurality of nodes for use during decoding, including at least one data generating node and at least one data checking node, and the storage circuits may store status information associated with the nodes, the status information indicating when each corresponding node is locked or unlocked. During decoding operations, the decoder circuit may set the status information to lock one or more of the nodes based on one or more locking conditions, and may cease decoding based on one or more ceasing conditions. The decoder circuit may locks a data generating node when a corresponding calculated value meets a particular condition, and may lock a data checking node when all data generating nodes associated with it are locked.

公开(公告)号：US20160204802A1

公开(公告)日：2016-07-14

申请号：US15075255

申请日：2016-03-21

Applicant: Maxlinear, Inc.

Inventor： Mingrui Zhu ,  Curtis Ling ,  Timothy Gallagher

IPC: H03M13/11

CPC classification number: H03M13/1114 ,  H03M13/1111 ,  H03M13/1125 ,  H03M13/1128 ,  H03M13/1131 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/1165 ,  H03M13/616 ,  H03M13/6505 ,  H04L1/0045

Abstract: In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node.

Abstract translation: 在本公开的示例实现中，在低位奇偶校验（LDPC）解码器的消息传送期间，在第一比特组解码期间，可以在第一可变节点达到确定阈值的比特值概率时锁定第一可变节点 并且在连接到第一校验节点被锁定的所有变量节点上锁定第一校验节点。 所述LDPC解码器可以在所述LDPC解码器的所有可变节点被锁定，所述LDPC解码器的所有校验节点被锁定，达到最大迭代次数或达到超时之后，停止解码所述第一组位。 在第一可变节点被锁定的第一组比特的解码的特定迭代期间，LDPC解码器可以避免为锁定的第一可变节点生成比特值概率。

公开(公告)号：US20150124915A1

公开(公告)日：2015-05-07

申请号：US14590250

申请日：2015-01-06

Applicant: Maxlinear, Inc.

Inventor： Pawandeep Taluja ,  Mingrui Zhu ,  Xuefeng Chen ,  Anand Anandakumer ,  Sheng Ye ,  Timothy Leo Gallagher

IPC: H03M1/06 ,  H04L7/00 ,  H03M1/12 ,  H04L25/08

CPC classification number: H03M1/0612 ,  H03M1/1009 ,  H03M1/1038 ,  H03M1/1215 ,  H03M1/50 ,  H04L7/0087 ,  H04L25/08 ,  H04W56/00

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

Abstract translation: 用于时间交织的模数转换器定时失配校准和补偿的方法和系统可以包括在芯片上接收模拟信号，利用时间交织的模数转换器（ADC）将模拟信号转换成数字信号， 并且通过估计期望的数字输出信号和阻塞信号之间的复耦合系数来减少由时间交错ADC中的定时偏移产生的阻塞信号。 解相关算法可以包括对称自适应去相关算法。 所接收的模拟信号可以由芯片上的校准音发生器产生。 混叠信号可以与来自乘法器的输出信号相加。 复数耦合系数可以利用求和信号上的去相关算法来确定。 乘法器可以被配置为利用所确定的复耦合系数来消除阻塞信号。

公开(公告)号：US20190123946A1

公开(公告)日：2019-04-25

申请号：US16113527

申请日：2018-08-27

Applicant: MaxLinear, Inc.

Inventor： Mingrui Zhu ,  Arun Kedambadi ,  Seung Chul Hong ,  Anand Anandakumar

IPC: H04L27/26 ,  H04L25/02

CPC classification number: H04L27/2605 ,  H04L25/0216 ,  H04L25/0222 ,  H04L25/0226 ,  H04L27/2607 ,  H04L27/2647 ,  H04L27/2655

Abstract: Methods and systems are provided for adaptive guard interval (GI) combining. A signal carrying a symbol that is preceded by a guard interval (GI) that includes a portion of the symbol may be received, and a portion of the GI that is free from inter-symbol interference (ISI) may be determined. Only a part of the ISI-free portion of the GI may be selected. The selected part of the ISI-free portion of the GI may be less than a whole of the ISI-free portion. The selection may be configured based on a parameter that is applied to a function used in extracting the symbol. The parameter may be a timing adjustment, relative to a start of the symbol, applied to the function when extracting the symbol. Only the part of the ISI-free portion of the GI may then be extracted and combined with a corresponding portion of the symbol.