Invention Grant
- Patent Title: Debug architecture
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Application No.: US15617953Application Date: 2017-06-08
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Publication No.: US09928361B2Publication Date: 2018-03-27
- Inventor: Andrew Brian Thomas Hopkins , Arnab Banerjee , Stephen John Barlow , Klaus Dieter McDonald-Maier
- Applicant: UltraSoC Technologies Ltd.
- Applicant Address: GB Cambridge
- Assignee: UltraSoC Technologies Ltd.
- Current Assignee: UltraSoC Technologies Ltd.
- Current Assignee Address: GB Cambridge
- Agency: Haynes Beffel & Wolfeld LLP
- Priority: GB1212181.0 20120709
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F21/44 ; G06F21/62 ; G01R31/317 ; G06F12/14 ; G06F11/34

Abstract:
Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.
Public/Granted literature
- US20170277883A1 DEBUG ARCHITECTURE Public/Granted day:2017-09-28
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