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公开(公告)号：US09928361B2
公开(公告)日：2018-03-27
申请号：US15617953
申请日：2017-06-08
Applicant: UltraSoC Technologies Ltd.
Inventor： Andrew Brian Thomas Hopkins , Arnab Banerjee , Stephen John Barlow , Klaus Dieter McDonald-Maier
CPC classification number: G06F21/44 , G01R31/31705 , G01R31/31719 , G06F11/348 , G06F21/62 , G06F2201/835 , G06F2201/86 , G06F2201/88
Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.
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Patent Agency Ranking
公开(公告)号：US20140013421A1
公开(公告)日：2014-01-09
申请号：US13938098
申请日：2013-07-09
Applicant: UltraSoC Technologies Ltd.
Inventor： Andrew Brian Thomas Hopkins , Arnab Banerjee , Stephen John Barlow , Klaus Dieter McDonald-Maier
IPC: G06F21/44
CPC classification number: G06F21/44 , G01R31/31705 , G01R31/31719 , G06F11/348 , G06F21/62 , G06F2201/835 , G06F2201/86 , G06F2201/88
Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.
Abstract translation: 大致描述了一种限制调试控制器访问集成电路芯片上的架构的方法，所述调试架构包括访问控制器，多个外围电路和共享集线器，共享集线器可由访问控制器访问，以及 所述多个外围电路，所述方法包括：在所述访问控制器处，认证所述调试控制器; 在访问控制器处，在认证之后向调试控制器分配一组访问权限，授予调试控制器部分访问调试体系结构的一组访问权限; 并且在分配了一组访问权限之后，允许调试控制器访问该组访问权限所允许的调试架构。
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公开(公告)号：US09703944B2
公开(公告)日：2017-07-11
申请号：US13938098
申请日：2013-07-09
Applicant: UltraSoC Technologies Ltd.
Inventor： Andrew Brian Thomas Hopkins , Arnab Banerjee , Stephen John Barlow , Klaus Dieter McDonald-Maier
CPC classification number: G06F21/44 , G01R31/31705 , G01R31/31719 , G06F11/348 , G06F21/62 , G06F2201/835 , G06F2201/86 , G06F2201/88
Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.
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公开(公告)号：US20170277883A1
公开(公告)日：2017-09-28
申请号：US15617953
申请日：2017-06-08
Applicant: UltraSoC Technologies Ltd.
Inventor： Andrew Brian Thomas Hopkins , Arnab Banerjee , Stephen John Barlow , Klaus Dieter McDonald-Maier
IPC: G06F21/44 , G01R31/317 , G06F21/62 , G06F11/34
CPC classification number: G06F21/44 , G01R31/31705 , G01R31/31719 , G06F11/348 , G06F21/62 , G06F2201/835 , G06F2201/86 , G06F2201/88
Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.
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公开(公告)号：US20160356841A1
公开(公告)日：2016-12-08
申请号：US15241805
申请日：2016-08-19
Applicant: UltraSoC Technologies Ltd.
Inventor： Andrew Brian Thomas Hopkins , Arnab Banerjee , Stephen John Barlow , Klaus Dieter Mcdonald-Maier
IPC: G01R31/28 , G01R31/317
CPC classification number: G01R31/2884 , G01R31/31705 , G01R31/31719 , G06F11/27 , G06F11/348 , G06F21/44 , G06F21/62 , G06F21/85 , G06F2201/835 , G06F2201/86 , G06F2201/88
Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.
Abstract translation: 大致描述了一种限制调试控制器访问集成电路芯片上的架构的方法，所述调试架构包括访问控制器，多个外围电路和共享集线器，共享集线器可由访问控制器访问，以及 所述多个外围电路，所述方法包括：在所述访问控制器处，认证所述调试控制器; 在访问控制器处，在认证之后向调试控制器分配一组访问权限，授予调试控制器部分访问调试体系结构的一组访问权限; 并且在分配了一组访问权限之后，允许调试控制器访问该组访问权限所允许的调试架构。
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公开(公告)号：US09927486B2
公开(公告)日：2018-03-27
申请号：US15241805
申请日：2016-08-19
Applicant: UltraSoC Technologies Ltd.
Inventor： Andrew Brian Thomas Hopkins , Arnab Banerjee , Stephen John Barlow , Klaus Dieter Mcdonald-Maier
CPC classification number: G01R31/2884 , G01R31/31705 , G01R31/31719 , G06F11/27 , G06F11/348 , G06F21/44 , G06F21/62 , G06F21/85 , G06F2201/835 , G06F2201/86 , G06F2201/88
Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.
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