Invention Grant
- Patent Title: Method of forming low height split gate memory cells
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Application No.: US15594883Application Date: 2017-05-15
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Publication No.: US09972493B2Publication Date: 2018-05-15
- Inventor: Chien-Sheng Su , Jeng-Wei Yang , Man-Tang Wu , Chun-Ming Chen , Hieu Van Tran , Nhan Do
- Applicant: Silicon Storage Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: DLA Piper LLP (US)
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/28 ; H01L21/306 ; G11C16/04 ; H01L29/772 ; H01L29/423

Abstract:
A method of forming a memory device that includes forming a first insulation layer on a semiconductor substrate, forming a conductive material layer on the first insulation layer, forming an insulation block on the conductive material layer, forming an insulation spacer along a side surface of the insulation block and on the conductive material layer, etching the conductive material layer to form a block of the conductive material disposed directly under the insulation block and the insulation spacer, removing the insulation spacer, forming a second insulation layer having a first portion wrapping around an exposed upper edge of the block of the conductive material and a second portion disposed on a first portion of the first insulation layer over the substrate, and forming a conductive block insulated from the block of the conductive material by the second insulation layer and from the substrate by the first and second insulation layers.
Public/Granted literature
- US20180040482A1 Method Of Forming Low Height Split Gate Memory Cells Public/Granted day:2018-02-08
Information query
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