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    Temperature compensation rc oscillator signal processing asic using source bulk voltage of the Mosfet
    3.
    发明专利
    Temperature compensation rc oscillator signal processing asic using source bulk voltage of the Mosfet 审中-公开

    公开(公告)号：JP2013504263A

    公开(公告)日：2013-02-04

    申请号：JP2012528064

    申请日：2010-09-02

    Applicant: エス3シー インコーポレイテッドS3C Inc.

    Inventor： シュ，ツィーネン

    IPC: H03K3/354 ,  H03B5/20 ,  H03K4/501

    CPC classification number: H03L1/022 ,  H03K3/011 ,  H03K3/03 ,  H03K3/354 ,  H03K4/502

    Abstract: A temperature compensated CMOS RC oscillator circuit changes the source-bulk voltage to stabilize the MOSFET's threshold voltage variation over temperature using a resistor and temperature-correlated bias current. The MOSFET's source is connected to ground through a resistor. This temperature-correlated bias current also runs through this resistor. When temperature increases, the bias current also increases, which increases the MOSFET's source-bulk voltage. The increased source-bulk voltage helps to stabilize the threshold voltage of MOSFET at high temperature. A power saving logic is also embedded in this oscillator to achieve higher frequency at lower power consumption. In the present invention, there is no high gain op amp or high speed comparator, which makes the resultant oscillator to be low power design and which can be integrated into a single chip with other system.

    Smart diagnosis and protection circuits for ASIC wiring fault conditions
    7.
    发明授权
    Smart diagnosis and protection circuits for ASIC wiring fault conditions 有权
    智能诊断和保护电路，用于ASIC接线故障条件

    公开(公告)号：US09054517B1

    公开(公告)日：2015-06-09

    申请号：US13829532

    申请日：2013-03-14

    Applicant: S3C, Inc.

    Inventor： Zhineng Zhu

    IPC: H02H3/00 ,  H02H9/04

    CPC classification number: H02H9/04 ,  H02H11/003 ,  H02H11/006

    Abstract: An application specific integrated circuit (ASIC) is disclosed. The ASIC comprises an internal circuit coupled between a power line and ground and an output buffer coupled to the internal circuit; wherein the output buffer provides an output signal. The ASIC includes a fault detection circuit coupled between the power line and ground; and a first protection block configured to receive a first control signal from the fault detection circuit. The first switch is coupled to the power line, the output buffer and the internal circuit. The first protection block prevents current from flowing between the power line and ground when a fault condition is detected. The ASIC further includes a second protection block configured to receive a second control signal from the fault detection circuit, wherein the second protection block is coupled to the output signal, the power line and ground. The second protection block prevents current from flowing between the power line and ground or the power line and the output line when a fault condition is detected.

    Abstract translation: 公开了专用集成电路（ASIC）。 ASIC包括耦合在电力线和地之间的内部电路和耦合到内部电路的输出缓冲器; 其中所述输出缓冲器提供输出信号。 ASIC包括耦合在电力线和地之间的故障检测电路; 以及被配置为从故障检测电路接收第一控制信号的第一保护块。 第一个开关耦合到电源线，输出缓冲器和内部电路。 当检测到故障条件时，第一个保护块防止电流在电源线和地之间流动。 ASIC还包括被配置为从故障检测电路接收第二控制信号的第二保护块，其中第二保护块耦合到输出信号，电力线和地。 当检测到故障条件时，第二保护模块防止电流在电源线与地之间或电源线和输出线之间流动。

    PROCESS FOR MINIMIZING CHIPPING WHEN SEPARATING MEMS DIES ON A WAFER
    8.
    发明申请
    PROCESS FOR MINIMIZING CHIPPING WHEN SEPARATING MEMS DIES ON A WAFER 审中-公开
    在微波炉上分离MEMS表面时最小化流动的方法

    公开(公告)号：WO2011140143A1

    公开(公告)日：2011-11-10

    申请号：PCT/US2011/035065

    申请日：2011-05-03

    Applicant: S3C. INC. ,  HORTON, Roger ,  HUSSAIN, Javed

    Inventor： HORTON, Roger ,  HUSSAIN, Javed

    IPC: H01L23/58

    CPC classification number: B81B7/0058 ,  B81C1/00888 ,  B81C2201/053 ,  G01L9/0055 ,  H01L21/78

    Abstract: A method for separating a plurality of dies on a Micro-Electro-Mechanical System (MEMS) wafer comprising scribing a notch on a first side of the wafer between at least two of the plurality of dies on a first surface and depositing a metal on the first surface of the plurality of dies. The method further comprises scribing a second side of the wafer between at least two of the plurality of dies from a second surface thereof through the notch. The first side and second side are substantially parallel and opposite each other and the first surface and the second surface are substantially parallel and opposite each other. In a process in accordance with the present invention, a method to minimize chipping of the bonding portion of a MEMs device during sawing of the wafer is provided, which minimally affects the process steps associated with separating the die on a wafer.

    Abstract translation: 一种用于在微电子机械系统（MEMS）晶片上分离多个管芯的方法，包括在第一表面上的多个管芯中的至少两个之间划定晶片的第一侧上的凹口，并在其上沉积金属 多个管芯的第一表面。 该方法还包括在多个管芯中的至少两个从其第二表面通过切口划分晶片的第二侧。 第一侧面和第二侧面基本上平行且彼此相对，并且第一表面和第二表面基本上平行且彼此相对。 在根据本发明的方法中，提供了一种在晶片切割期间最小化MEM器件的结合部分的碎裂的方法，其最小程度地影响与在晶片上分离晶片相关的工艺步骤。

    MEDIA-COMPATIBLE ELECTRICALLY ISOLATED PRESSURE SENSOR FOR HIGH TEMPERATURE APPLICATIONS
    10.
    发明公开
    MEDIA-COMPATIBLE ELECTRICALLY ISOLATED PRESSURE SENSOR FOR HIGH TEMPERATURE APPLICATIONS 审中-公开
    介质兼容电隔离的压力传感器适用于高温

    公开(公告)号：EP2404150A1

    公开(公告)日：2012-01-11

    申请号：EP10749253.0

    申请日：2010-03-03

    Applicant: S3C, Inc.

    Inventor： SUMINTO, James, Tjanmeng ,  YUNUS, Mohammad

    IPC: G01L9/06

    CPC classification number: B81C1/00158 ,  G01L9/0042 ,  G01L9/0055 ,  G01L19/147

    Abstract: A pressure sensor is described with sensing elements electrically and physically isolated from a pressurized medium. An absolute pressure sensor has a reference cavity, which can be at a vacuum or zero pressure, enclosing the sensing elements. The reference cavity is formed by bonding a recessed cap wafer with a gauge wafer having a micromachined diaphragm. Sensing elements are disposed on a first side of the diaphragm. The pressurized medium accesses a second side of the diaphragm opposite to the first side where the sensing elements are disposed. A spacer wafer may be used for structural support and stress relief of the gauge wafer. In one embodiment, vertical through-wafer conductive vias are used to bring out electrical connections from the sensing elements to outside the reference cavity. In an alternative embodiment, peripheral bond pads on the gauge wafer are used to bring out electrical connections from the sensing elements to outside the reference cavity

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