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公开(公告)号：EP3940922A1
公开(公告)日：2022-01-19
申请号：EP21184170.5
申请日：2021-07-07
Applicant: STMicroelectronics (Shenzhen) R&D Co., Ltd.
Inventor： WANG, Jiasheng
Abstract: A method and system for operating a power circuit capable of transmitting and receiving wireless power. The method includes determining that the power circuit is operating in receive mode, and, based thereon, having a first equivalent capacitance. The method further includes determining that the power circuit is operating in the transmit mode, and, based thereon, having a second equivalent capacitance. The first equivalent capacitance being different than the second equivalent capacitance.
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公开(公告)号：EP3859361A1
公开(公告)日：2021-08-04
申请号：EP21151081.3
申请日：2021-01-12
Inventor： PISELLO, Ignazio , WANG, Yu Yong , ARENA, Dario , LIU, Qi Yu
IPC: G01R31/3185
Abstract: An electronic circuit (10') comprises:
- a combinational circuit block (100) having a set of input pins (IN1, ..., INn) configured to receive input digital signals and a set of output pins (OUT1, ..., OUTm) configured to provide output digital signals as a function of the input digital signals received,
- a test input pin (SCAN_IN) configured to receive a test input signal and a test output pin (SCAN_OUT) configured to provide a test output signal as a function of the test input signal received,
- a set of scan registers (SRI, SR2, SR3) selectively (SE) couplable (M1, M2, M3) either to the combinational circuit block (100) or to one another so as to form a scan chain of scan registers serially coupled between the test input pin (SCAN_IN) and the test output pin (SCAN_OUT), the scan registers in the set of scan registers being sensitive to a clock signal (CLK), and
- at least one input register (HI, H2) coupled between the test input pin (SCAN_IN) and a first scan register (SRI) of said scan chain, wherein the at least one input register (HI, H2) is sensitive to an inverted replica (20) of said clock signal (CLK).
The scan registers in the set of scan registers (SRI, SR2, SR3) are active on one of the rising edges or falling edges of said clock signal (CLK) provided thereto, and said at least one input register (HI, H2) is active on the other of the rising edges or falling edges of said clock signal (CLK).-
公开(公告)号：EP3442121A1
公开(公告)日：2019-02-13
申请号：EP18184122.2
申请日：2018-07-18
Inventor： BOTTI, Edoardo , BRAMBILLA, Davide Luigi , LIN, Hong Wu
IPC: H03K17/0814 , G05F3/08
Abstract: A circuit includes:
- a power field effect transistor (T) having a gate configured to be driven (D) via a drive signal (Vsupply), the field effect transistor (T) having a drain-source voltage drop indicative of the intensity of a current (Id) flowing in the current path through the field effect transistor (T), and
- a pair of sensing transistors (ST1, ST2), including:
- i) a first sensing field effect transistor (ST1) arranged with its drain and gate coupled with the drain and the gate of the field effect transistor (T), respectively,
- ii) a second sensing field effect transistor (ST2) having a gate configured for receiving a replica of said drive signal (Vsupply), the second sensing field effect transistor (ST2) arranged with its current path in series with the current path of the first sensing field effect transistor (ST1).
A sensing signal (Vo) at a sensing node (S) between the first sensing field effect transistor (ST1) and the second sensing field effect transistor (ST2) is indicative of the current intensity (Id) flowing in the current path of the field effect transistor (T).-
公开(公告)号：EP4207588A1
公开(公告)日：2023-07-05
申请号：EP22215802.4
申请日：2022-12-22
Applicant: STMicroelectronics (Shenzhen) R&D Co., Ltd.
Inventor： COSTANZO, Dino , XU, Xiyu , CAI, Chengpan
Abstract: An apparatus includes a first inverter (101) configured to drive a first motor (111) having a plurality of phases, the first inverter (101) comprising a plurality of inverter legs, each of which is coupled to a corresponding phase of the first motor (111), a second inverter (102) configured to drive a second motor (112) having a plurality of phases, the second inverter (102) comprising a plurality of inverter legs, each of which is coupled to a corresponding phase of the second motor (112), and a first current sensor (S1) configured to sense currents flowing in the first inverter (101) and the second inverter (102), wherein the first current sensor (S1) is shared by at least by two inverter legs.
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公开(公告)号：EP4007166A1
公开(公告)日：2022-06-01
申请号：EP21202997.9
申请日：2021-10-15
Inventor： LIN, Mr. Hong Wu , GONANO, Mr. Giovanni , BOTTI, Mr. Edoardo
Abstract: In an embodiment, a method for shaping a PWM signal includes: receiving an input PWM signal (V pwm _ out ); generating an output PWM signal (V pwm _ pre ) based on the input PWM signal by: when the input PWM signal (V pwm_out ) transitions with a first edge of the input PWM signal, transitioning the output PWM signal (V pwm _ pre ) with a first edge of the output PWM signal; and when the input PWM signal (V pwm_out ) transitions with a second edge before the first edge of the output PWM signal (V pwm_pre ) transitions, delaying a second edge of the output PWM signal (V pwm_pre ) based on the first edge of the output PWM signal.
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Patent Agency Ranking
公开(公告)号：EP3091659A1
公开(公告)日：2016-11-09
申请号：EP15197508.3
申请日：2015-12-02
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd
Inventor： LIU, QiYu , LIN, Hong Wu
IPC: H03F3/217
CPC classification number: H03F3/2173 , H03F2200/03 , H03F2200/114
Abstract: A class-D amplifier (100) includes a signal processing block (140). The signal processing block generates a first processed signal (Vp) representing a difference between a first differential signal and a second differential signal, when a duty cycle of the first differential signal is greater than that of the second differential signal. The signal processing block generates the first processed signal representing a reference DC level, when the duty cycle of the first differential signal is less than that of the second differential signal. A second processed signal (Vn) representing a difference between the second differential signal and the first differential signal is generated when the duty cycle of the second differential signal is greater than that of the first differential signal, and the second processed signal representing the reference DC level is generated when the duty cycle of the second differential signal is less than that of the first differential signal.
Abstract translation: D类放大器（100）包括：信号处理块（140）。 信号处理块基因率表示第一差分信号和第二差分信号，当第一差分信号的占空比比所述第二差分信号的更大之间的差的第一经处理的信号（VP）。 信号处理块基因率表示参考DC电平的第一处理后的信号，当第一差分信号的占空比小于所述第二差分信号的。 生成表示所述第二差分信号，并将所述第一差分信号之间的差的第二经处理的信号（VN）当将第二差分信号的占空比大于第一差分信号的更大，并且所述第二处理后的信号代表的参考DC 产生电平。当将第二差分信号的占空比小于该第一差分信号的。
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公开(公告)号：EP4231122A1
公开(公告)日：2023-08-23
申请号：EP23156559.9
申请日：2023-02-14
Inventor： CHEN, Bowei , DING, Yue , SUN, Guodong
IPC: G06F3/041
Abstract: A method for operating an electronic device includes detecting, by a touchscreen controller, a touch point on a touchscreen; determining, by the touchscreen controller, coordinates of the touch point; scaling, by the touchscreen controller, up the coordinates of the touch point to obtain scaled up coordinates by overwriting a reserved portion of a touch event protocol with additional information corresponding to the coordinates of the touch point; reporting, by the touchscreen controller, the scaled up coordinates of the touch point to an application processor; and determining, by the application processor, the coordinates of the touch point with an increased resolution by converting the scaled up coordinates into a floating point value.
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公开(公告)号：EP3972086A1
公开(公告)日：2022-03-23
申请号：EP21192692.8
申请日：2021-08-24
Inventor： ZAHO, Wenhe , WANG, Jiasheng
Abstract: A method for modulating a signal including operating a circuit in a first arrangement during a first operating interval and switching the circuit between the first arrangement and a second arrangement during a first modulation interval to vary a load on the circuit to produce a first amplitude shift keying (ASK) signal. The method further includes detecting a voltage on the circuit crossing a threshold level and operating the circuit in the second arrangement during a second operating interval. The method also includes switching the circuit between the second arrangement and the first arrangement during a second modulation interval to vary the load on the circuit to produce a second ASK signal.
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公开(公告)号：EP3739754A1
公开(公告)日：2020-11-18
申请号：EP20171041.5
申请日：2020-04-23
Applicant: STMicroelectronics (Shenzhen) R&D Co., Ltd.
Inventor： WEN, Mr. Kelvin aka Jian , LI, Mr. Hong Xia , YANG, Mr. Mei
Abstract: In an embodiment, a power switch controller (204) for driving a back-to-back power switch (102) includes: an amplifier (206) having a supply terminal configured to receive a supply voltage (Vcc), an output configured to be coupled to a gate terminal (G) of the back-to-back power switch (102), a first input configured to be coupled a source terminal (S) of the back-to-back power switch (102), and a second input coupled to the output of the amplifier (206). The amplifier is configured to generate an output voltage at the output of the amplifier, the output voltage being an offset voltage higher than a voltage at the first input of the amplifier (206).
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公开(公告)号：EP3661053A1
公开(公告)日：2020-06-03
申请号：EP19211832.1
申请日：2019-11-27
Applicant: STMicroelectronics (Shenzhen) R&D Co., Ltd.
Inventor： LI, Xiang Sheng , DU, Ru Feng
Abstract: An audio amplifier (400) includes: a buck controller (406, 408) configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller (406, 408) is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.
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