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    Reduced power load/store queue searching mechanism
    1.
    发明公开
    Reduced power load/store queue searching mechanism 有权
    Lade- / Speicherwarteschlangensuch机制有限公司Energieverbrauch

    公开(公告)号：EP2202637A1

    公开(公告)日：2010-06-30

    申请号：EP09180317.1

    申请日：2009-12-22

    Applicant: STMicroelectronics (Beijing) R&D Co. Ltd.

    Inventor： Wang, Kai-Feng ,  Sun, Hong-Xia ,  Wu, Yong-Qiang

    IPC: G06F9/38 ,  G06F1/32

    CPC classification number: G06F9/3834 ,  G06F9/3824 ,  G06F9/3855

    Abstract: A comparison circuit can reduce the amount of power consumed when searching a load queue or a store queue of a microprocessor. Some embodiments of the comparison circuit use a comparison unit that performs an initial comparison of addresses using a subset of the address bits. If the initial comparison results In a match, a second comparison unit can be enabled to compare another subset of the address bits.

    Abstract translation: 比较电路可以减少在搜索微处理器的加载队列或存储队列时消耗的功率量。 比较电路的一些实施例使用比较单元，其使用地址位的子集来执行地址的初始比较。 如果初始比较结果在匹配中，可以使第二比较单元能够比较另一个地址位的子集。

    CIRCULAR BUFFER ACCESSING DEVICE, SYSTEM AND METHOD
    2.
    发明公开
    CIRCULAR BUFFER ACCESSING DEVICE, SYSTEM AND METHOD 审中-公开

    公开(公告)号：EP4216056A1

    公开(公告)日：2023-07-26

    申请号：EP22211166.8

    申请日：2022-12-02

    Applicant: STMicroelectronics (Beijing) R&D Co. Ltd. ,  STMicroelectronics S.r.l.

    Inventor： JIAO, Xiao Kang ,  DE AMBROGGI, Fabio Giuseppe

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/355

    Abstract: A device includes a circular buffer, which, in operation, is organized into a plurality of subsets of buffers, and control circuitry coupled to the circular buffer. The control circuitry, in operation, receives a memory load command (404) to load a set of data into the circular buffer. The memory load command (404) has an offset parameter (408) indicating a data offset and a subset parameter (410) indicating a subset of the plurality of subsets into which the circular buffer is organized. The control circuitry responds to the command by identifying a set of buffer addresses (412) of the circular buffer based on a value of the offset parameter (408) and a value of the subset parameter (410), and loading the set of data (414) into the circular buffer using the identified set of buffer addresses (412).

    Sleep mode control for real-time services in broadband wireless access communication systems
    6.
    发明公开
    Sleep mode control for real-time services in broadband wireless access communication systems 审中-公开
    Breitband-Funkzugangs-Kommunikationssystemen的SchlafmodussteuerungfürEchtzeitdienste

    公开(公告)号：EP1954078A1

    公开(公告)日：2008-08-06

    申请号：EP08150758.4

    申请日：2008-01-29

    Applicant: STMicroelectronics (Beijing) R&D Co. Ltd.

    Inventor： Zhu, Hongfei ,  Yao, Yanling ,  Sun, Guobin

    IPC: H04Q7/32

    CPC classification number: H04W52/0216 ,  H04W28/24 ,  Y02D70/142 ,  Y02D70/146

    Abstract: Consideration of Quality of Service is taken into account during the establishment of a sleep cycle in a mobile station providing real-time services. Upon the mobile station's identification of a need for a real-time service to enter into sleep mode, a request conveying that need is sent to the base station. The base station replies with a start frame number and other sleep parameters. Thereafter the mobile station enters sleep mode comprising sleep intervals interleaved with listening intervals. To prevent transmission packets from being buffered at the mobile station for an excessive period of time due to attempts to transmit packets to the base station during a sleep interval, the length of the sleep interval is set so as not to exceed the maximum latency value reflecting the QoS of the real-time service negotiated during establishment of the real-time services.

    Abstract translation: 在提供实时服务的移动台建立睡眠周期期间，考虑服务质量。 当移动台识别到需要进入睡眠模式的实时服务时，将需要的请求发送到基站。 基站用起始帧号和其他睡眠参数进行回复。 此后，移动台进入休眠模式，其包括与侦听间隔交错的睡眠间隔。 为了防止在睡眠间隔期间由于尝试向基站发送分组而在移动台处被缓冲的传输分组过长的时间段，睡眠间隔的长度被设置为不超过反映 在建立实时业务时协商的实时业务的QoS。

    Decoding method for tail-biting convolutional codes using a search-depth Viterbi algorithm
    7.
    发明公开
    Decoding method for tail-biting convolutional codes using a search-depth Viterbi algorithm 有权
    DekodierverfahrenfürTail-Biting-Faltungscodes mittels Viterbi-Algorithmus mit Suchtiefe

    公开(公告)号：EP1841116A2

    公开(公告)日：2007-10-03

    申请号：EP07251368.2

    申请日：2007-03-29

    Applicant: STMicroelectronics (Beijing) R&D Co. Ltd.

    Inventor： Shi, Wuxian c/o Beijing Office East Unit, ,  Du, Juan c/o Beijing Office East Unit, ,  Ge, Yiqun c/o Beijing Office East Unit, ,  Sun, Guobin c/o Beijing Office East Unit,

    IPC: H04L1/00 ,  H03M13/41

    CPC classification number: H03M13/3938 ,  H03M13/413 ,  H03M13/6362 ,  H03M13/6502 ,  H03M13/6505 ,  H04L1/0054 ,  H04L1/0059

    Abstract: A method for decoding tail-biting convolutional codes. The method includes initializing a correction depth, selecting a first starting state from a set of encoding states, and initializing a metric value for the selected starting state as zero and the other states as infinity. The input bit stream is read and a Search Depth Viterbi algorithm (SDVA) is performed to determine path metrics and identify a minimum-metric path. The ending state for the minimum-metric path is determined and the output for this ending state is identified as "previous output." A second starting state is set to the ending state of the minimum-metric path, and symbols equal to the correction depth from the previous output are read. The SDVA is performed on the second set of read symbols to generate a corrected output. A decoded output is generated by replacing symbols at the beginning of the previous output with the corrected output.

    Abstract translation: 一种用于解码尾巴卷积码的方法。 该方法包括初始化校正深度，从一组编码状态中选择第一起始状态，以及将所选择的起始状态的度量值初始化为零，将其他状态初始化为无穷大。 读取输入比特流，并执行搜索深度维特比算法（SDVA）以确定路径度量并识别最小度量路径。 确定最小度量路径的结束状态，将该结束状态的输出识别为“先前输出”。 将第二起始状态设置为最小度量路径的结束状态，并且读取等于来自先前输出的校正深度的符号。 在第二组读符号上执行SDVA以产生校正输出。 通过使用校正输出替换先前输出开始处的符号来产生解码输出。

    Reducing instruction collisions in a processor
    9.
    发明公开
    Reducing instruction collisions in a processor 有权
    einem Prozessor的Verringerung der Befehlskollisionen

    公开(公告)号：EP2207089A1

    公开(公告)日：2010-07-14

    申请号：EP09180314.8

    申请日：2009-12-22

    Applicant: STMicroelectronics (Beijing) R&D Co. Ltd.

    Inventor： Wang, Kai-Feng ,  Sun, Hong- Xia ,  Zhu, Peng-Fei ,  Wu, Yong-Qiang

    IPC: G06F9/38

    CPC classification number: G06F9/3836 ,  G06F9/3855

    Abstract: An embodiment of a technique for selecting instructions for execution from an issue queue at multiple function units while reducing the chances of instruction collisions. Each function unit in a processor may include a selection logic circuit that selects a specific instruction from the issue queue for execution. In order to avoid instruction collision, a function unit may have a selection logic circuit that may select two instructions from an instruction queue: one according to a first selection technique and one according to a second selection technique. Then, by comparing the instruction selected by the first selection technique to the instruction selected by the selection logic circuit of another function unit, the instruction selected by the second technique may be used instead if there will be an instruction collision because the instruction selected by the first selection technique is the same as the instruction selected at a different function unit.

    Abstract translation: 用于在减少指令冲突的机会的同时从多个功能单元的发布队列中选择用于执行的指令的技术的实施例。 处理器中的每个功能单元可以包括从发布队列中选择特定指令以执行的选择逻辑电路。 为了避免指令冲突，功能单元可以具有可以从指令队列中选择两个指令的选择逻辑电路：一个根据第一选择技术和根据第二选择技术的指令。 然后，通过将由第一选择技术选择的指令与由另一功能单元的选择逻辑电路选择的指令进行比较，可以使用由第二技术选择的指令来代替，否则将产生指令冲突，因为由 第一选择技术与在不同功能单元处选择的指令相同。

    Time and frequency synchronization method for ofdma uplink receivers and base stations
    10.
    发明公开
    Time and frequency synchronization method for ofdma uplink receivers and base stations 有权
    时间和频率同步方法，用于上行链路OFDMA接收机和基站

    公开(公告)号：EP1826977A3

    公开(公告)日：2008-05-21

    申请号：EP07250818.7

    申请日：2007-02-28

    Applicant: STMicroelectronics (Beijing) R&D Co. Ltd.

    Inventor： Yiqun, Ge ,  Wuxian, Shi ,  Juan, Du

    IPC: H04L27/26

    CPC classification number: H04L27/2657 ,  H04L27/2662 ,  H04L27/2684 ,  H04L27/2691

    Abstract: A method, and components for performing such method, is provided for synchronizing multiple user signals in a multi-user communication system. An interference matrix is generated based on time delay and frequency offset information for the active users accessing an OFDMA uplink receiver. User signals are received from the active users and are segmented into blocks, and the interference matrix is applied to each of the blocks. The received user signal is OFDM demodulated and unused sub-carriers are discarded. Typically, the method includes also applying a factorization matrix formed by factoring a correction matrix created from the interference matrix and an inverse matrix formed based on the factoring results to the user signal blocks, e.g., the correction step includes multiplying each of the blocks from the user signal by each of these three matrices. The corrected user blocks are then concatenated to form a corrected vector signal.

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