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    TIME DOMAIN EQUALIZATION USING FREQUENCY DOMAIN OPERATIONS
    1.
    发明申请
    TIME DOMAIN EQUALIZATION USING FREQUENCY DOMAIN OPERATIONS 审中-公开
    使用频域操作的时域均衡

    公开(公告)号：WO2003098832A2

    公开(公告)日：2003-11-27

    申请号：PCT/BE2003/000087

    申请日：2003-05-19

    Applicant: STMICROELECTRONICS N.V. ,  STMICROELECTRONICS BELGIUM N.V. ,  PISONI, Fabio ,  HUG, Roland ,  BONAVENTURA, Marco

    Inventor： PISONI, Fabio ,  HUG, Roland ,  BONAVENTURA, Marco

    IPC: H04B3/23

    CPC classification number: H04B3/23 ,  H04L25/03012 ,  H04L25/03159 ,  H04L27/2647

    Abstract: An equalizer for a multi carrier transmission system, converts a transmitted multi carrier signal into sampled frequency domain signals, and suppresses time domain delay dispersion, on the sampled frequency domain signals. It exploits circulant decomposition of a Toeplitz matrix to enable the computationally heavy evaluation of a matrix multiplied by a vector, to be avoided. Increased precision arises from the frequency domain processing being equivalent to a longer time domain FIR filter than is normally practical. The amount of compensation for different carriers can be adjusted, which can lead to increased precision.

    Abstract translation: 一种用于多载波传输系统的均衡器，将所发送的多载波信号转换成采样的频域信号，并对采样的频域信号抑制时域延迟色散。 它利用Toeplitz矩阵的循环分解，使得可以计算重估计矩阵乘以向量，以避免。 与通常实际相比，频域处理相当于更长时间的FIR滤波器产生的精度提高。 可以调整不同载体的补偿量，从而提高精度。

    CUSTOMER FRAMEWORK FOR EMBEDDED APPLICATIONS
    2.
    发明申请
    CUSTOMER FRAMEWORK FOR EMBEDDED APPLICATIONS 审中-公开
    用于嵌入式应用的客户框架

    公开(公告)号：WO2004111840A2

    公开(公告)日：2004-12-23

    申请号：PCT/BE2004/000088

    申请日：2004-06-17

    Applicant: STMICROELECTRONICS BELGIUM N.V. ,  QUANTEN, Erik ,  JACOPS, Davy

    Inventor： QUANTEN, Erik ,  JACOPS, Davy

    IPC: G06F9/40

    CPC classification number: G06F8/36

    Abstract: The present invention provides a framework so that software can be embedded into a telecommunications semiconductor device such as an integrated circuit or into a chip. The framework is an API. The telecommunications device may support a telecommunications protocol, e.g. a wireless protocol such as BT. For example the BT Layers above an HCI can support different profiles and/or Applications. The semiconductor devices according to the present invention are particularly suitable for products where no host processor is available to provide the process engine to run the applications software. The semiconductor devices according to the present invention can include an ASIC, an integrated circuit, a multicarrier module (MCM) a printed circuit board or similar. Such devices may find advantageous use in small apparatus, e.g. wireless linked headphones.

    Abstract translation: 本发明提供了一种框架，使得软件可以嵌入诸如集成电路或芯片的电信半导体器件中。 框架是一个API。 电信设备可以支持电信协议，例如， 诸如BT的无线协议。 例如，HCI以上的BT层可以支持不同的配置文件和/或应用程序。 根据本发明的半导体器件特别适合于没有主处理器可用于提供处理引擎以运行应用软件的产品。 根据本发明的半导体器件可以包括ASIC，集成电路，多载波模块（MCM），印刷电路板等。 这样的装置可以在小型装置中发现有利的用途，例如， 无线连接耳机。

    Delay-compensated fractional-N frequency synthesizer
    4.
    发明申请
    Delay-compensated fractional-N frequency synthesizer 有权
    延迟补偿分数N频率合成器

    公开(公告)号：US20040196108A1

    公开(公告)日：2004-10-07

    申请号：US10737532

    申请日：2003-12-16

    Applicant: STMicroelectronics Belgium N.V.

    Inventor： Jan Frans Lucien Craninckx

    IPC: H03L007/00

    CPC classification number: H03L7/081 ,  H03L7/0893 ,  H03L7/1976

    Abstract: A Phase-Locked Loop is provided that includes a main loop, a calibration loop, and Control Logic. The main loop comprises, coupled in series, a Phase Frequency Detector, a Main Charge Pump, a Main Loop Filter, a Voltage Controlled Oscillator and a Frequency Divider. The calibration loop is coupled to the Phase Frequency Detector and comprises a Calibration Charge Pump and a Calibration Loop Filter. The Control Logic controls the Frequency Divider and receives a control input signal. A Reference Frequency Signal is coupled to the Phase Frequency Detector and the Control Logic, and a calibration signal is coupled to the calibration loop. Additionally, the main loop further comprises a delay generator controlled by the Control Logic and arranged to receive correction signals from the calibration loop and to send an output signal to the Phase Frequency Detector.

    Abstract translation: 提供了一个锁相环，包括主回路，校准回路和控制逻辑。 主回路包括串联耦合的相位检波器，主电荷泵，主回路滤波器，压控振荡器和分频器。 校准环路耦合到相位检波器，包括校准电荷泵和校准环路滤波器。 控制逻辑控制分频器并接收控制输入信号。 参考频率信号耦合到相位频率检测器和控制逻辑，并且校准信号耦合到校准环路。 此外，主回路还包括由控制逻辑控制的延迟发生器，并被布置成从校准环路接收校正信号并向相位检波器发送输出信号。

    Low frequency self-calibration of a PLL with multiphase clocks
    5.
    发明申请
    Low frequency self-calibration of a PLL with multiphase clocks 有权
    具有多相时钟的PLL的低频自校准

    公开(公告)号：US20040180638A1

    公开(公告)日：2004-09-16

    申请号：US10718256

    申请日：2003-11-20

    Applicant: STMicroelectronics Belgium N.V.

    Inventor： Jan Frans Lucien Craninckx

    IPC: H04B001/18

    CPC classification number: H03L7/18 ,  H03L7/081 ,  H03L7/0893 ,  H03L7/0996

    Abstract: A Phase-Locked Loop with multiphase clocks is provided. The Phase-Locked Loop includes a main loop, a calibration loop, and Control Logic. The main loop includes, coupled in series, a Phase Frequency Detector, a Main Charge Pump, a Main Loop Filter, a Multi-Phase Voltage Controlled Oscillator and a Phase-switching Fractional Divider. The calibration loop is coupled to the Phase Frequency Detector, and comprises a Calibration Charge Pump, a Multiplexer and Y Calibration Loop Filters, with Y being an integer. The Control Logic controls the Phase-Switching Fractional Divider and the Multiplexer. A Reference Frequency Signal is coupled to the Phase Frequency Detector and a Calibration Signal is coupled to the calibration loop. The main loop further comprises a Phase-adjusting Block coupled to a Demultiplexer. The Phase-adjusting Block is arranged so as to receive at least one correction signal from the calibration loop.

    Abstract translation: 提供了具有多相时钟的锁相环。 锁相环包括主回路，校准回路和控制逻辑。 主回路包括串联耦合的相位检波器，主电荷泵，主回路滤波器，多相电压控制振荡器和相位切换分数分频器。 校准环路耦合到相位检波器，并且包括校正电荷泵，多路复用器和Y校准环路滤波器，Y为整数。 控制逻辑控制相位切换分数分频器和多路复用器。 参考频率信号耦合到相位频率检测器，校准信号耦合到校准环路。 主环路还包括耦合到解复用器的相位调整块。 相位调整块被布置成从校准环路接收至少一个校正信号。

    Self-calibration of a PLL with multiphase clocks
    6.
    发明申请
    Self-calibration of a PLL with multiphase clocks 有权
    具有多相时钟的PLL的自校准

    公开(公告)号：US20040157577A1

    公开(公告)日：2004-08-12

    申请号：US10718257

    申请日：2003-11-20

    Applicant: STMicroelectronics Belgium N.V.

    Inventor： Jan Frans Lucien Craninckx

    IPC: H04B001/06 ,  H04B007/00 ,  H03D003/24

    CPC classification number: H03L7/0996 ,  H03L7/081 ,  H03L7/0891 ,  H03L7/18

    Abstract: A Phase-Locked Loop with multiphase clocks is provided. The Phase-Locked Loop includes a main loop, a calibration loop, and a Multiplexer. The main loop includes, coupled in series, a Phase Frequency Detector, a Main Charge Pump, a Main Loop Filter, a Multi-Phase Voltage Controlled Oscillator and a Phase-switching Fractional Divider. The calibration loop includes Y Calibration Loop Filters, with Y being an integer, coupled to the Multi-Phase Voltage Controlled Oscillator, and Control Logic for controlling the Phase-Switching Fractional Divider. The Multiplexer is coupled between an output of the Main Charge Pump and inputs of the Main Loop Filter and the Y Calibration Loop Filters. A Reference Frequency Signal is coupled to the Phase Frequency Detector, a control signal from the Control Logic is coupled to the Multiplexer, and a Calibration Signal is coupled to a control input of the Control Logic.

    Abstract translation: 提供了具有多相时钟的锁相环。 锁相环包括主回路，校准回路和多路复用器。 主回路包括串联耦合的相位检波器，主电荷泵，主回路滤波器，多相电压控制振荡器和相位切换分数分频器。 校准回路包括Y校准环路滤波器，Y为整数，耦合到多相电压控制振荡器，控制逻辑用于控制相位切换分数分频器。 多路复用器连接在主电荷泵的输出端和主回路滤波器和Y校准环路滤波器的输入端之间。 参考频率信号耦合到相位频率检测器，来自控制逻辑的控制信号耦合到多路复用器，校准信号耦合到控制逻辑的控制输入端。

    Mixer cell with a dynamic bleed circuit
    7.
    发明公开
    Mixer cell with a dynamic bleed circuit 有权
    Mischerzelle mit einem dynamischen Stromablasskreis

    公开(公告)号：EP2148432A1

    公开(公告)日：2010-01-27

    申请号：EP08161226.9

    申请日：2008-07-25

    Applicant: STMicroelectronics Belgium N.V.

    Inventor： Joos, Dieter c/o STMicroelectronics Belgium N.V. ,  Terryn, Steven c/o STMicroelectronics Belgium N.V.

    IPC: H03D7/14

    CPC classification number: H03D7/1441 ,  H03D7/1458 ,  H03D7/165 ,  H03D2200/0025 ,  H03D2200/0084 ,  H03D2200/0088

    Abstract: A mixer is described having a Gilbert cell structure including a first input and a second input for inputting an RF signal, a third input and a fourth input for inputting a local oscillator signal, a first output and a second output for outputting an IF signal, switches to convert the RF input to the IF output, and a dynamic bleed circuit for dynamically reducing the de-current of the switches at the switching-point. As the de-current of the switches is reduced at the point of commutation the 1/f-noise is also strongly reduced without degrading the linearity. The switching happens at twice the Local oscillator frequency.
    The DBC makes the circuit superior to static bleed current(SBC). When using static bleed current the dc current in the switches is continuously lower, leading to worse linearity
    The mixer also includes a common mode feedback circuit that feeds the common mode signal, optionally amplified to a common mode feedback control device that is in series between the dynamic bleed circuit and the supply voltage.

    Abstract translation: 描述了具有吉尔伯特单元结构的混频器，其包括用于输入RF信号的第一输入和第二输入，用于输入本地振荡器信号的第三输入和第四输入，用于输出IF信号的第一输出和第二输出， 开关将RF输入转换为IF输出，以及动态放电电路，用于动态降低开关点处开关的去电流。 由于开关的去电流在换向点处减小，所以在不降低线性的情况下，1 / f噪声也大大降低。 切换发生在本机振荡器频率的两倍。 DBC使电路优于静态放电电流（SBC）。 当使用静态放电电流时，开关中的直流电流不断降低，导致更差的线性度。混频器还包括一个共模反馈电路，馈送共模信号，可选地放大到共模反馈控制装置，该共模反馈控制装置串联在 动态放电电路和电源电压。

    A patching device for a processor
    9.
    发明公开
    A patching device for a processor 审中-公开
    用于处理器的修复装置

    公开(公告)号：EP1655667A3

    公开(公告)日：2008-10-29

    申请号：EP05447243.6

    申请日：2005-11-04

    Applicant: STMicroelectronics Belgium N.V.

    Inventor： Alexandre, Rudolph ,  Charlier, Vincent ,  Rahaga, Tiana ,  Vandersmissen, Yves

    IPC: G06F12/06

    CPC classification number: G06F9/30149 ,  G06F9/322 ,  G06F9/328 ,  G06F12/0638

    Abstract: A code patching device is provided for use with a processor having a read-only memory which stores instruction code and a further memory for storing patch code. A plurality of patch address registers each store an address, in the read-only memory, at which a patch is to be performed. A comparator compares the address of the read-only memory that is being accessed by the processor with the addresses stored in the registers. A control unit selects between code from the read-only memory or patch code from the further memory depending on the comparison. The code patching device can replace, on-the-fly, erroneous lines of code from the read-only memory by corrected ones. During an initialisation process the patch code is loaded into the further memory and the registers are loaded with the addresses which require patching.

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