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公开(公告)号：KR1019920006613B1
公开(公告)日：1992-08-10
申请号：KR1019880015983
申请日：1988-12-01
Applicant: 한국전자통신연구원
IPC: G06F9/30
Abstract: The delayed branch and the squashing branch are used dynamically to reduce the flushing of instructions in squashing time occured after the branch operation. The instruction fetch unit comprises an instruction fetch buffer unit (IFB) for storing one word instruction transmitted from an instruction cash memory, a memory (V) for storing the state of the instruction fetch buffer unit (IFB), an instruction register unit (IR) for receiving instruction transmitted from the instruction fetch buffer unit and the instruction fetch memory and for sending instruction to an instruction decoder, and a control logic unit (CNTL) for sending cash memory insturction to the instruction register unit when the instruction fetch buffer unit is empty.
Abstract translation: 动态地使用延迟分支和挤压分支以减少在分支操作之后发生的挤压时间中的指令的刷新。 指令提取单元包括用于存储从指令现金存储器发送的一个字指令的指令获取缓冲单元（IFB），用于存储指令获取缓冲单元（IFB）的状态的存储器（V）），指令寄存器单元 ），用于从指令获取缓冲器单元和指令获取存储器发送的指令以及用于向指令解码器发送指令的控制逻辑单元（CNTL），以及用于当指令获取缓冲器单元为 空。
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公开(公告)号：KR1019930000871B1
公开(公告)日：1993-02-08
申请号：KR1019890016416
申请日：1989-11-13
Applicant: 한국전자통신연구원
Abstract: The integrated circuit (IC) for providing the latch of simple structure includes: a plurality of memory columns for storing the input data; a memory including a plurality of output decoders, which are connected to the respective memory columns; an address decoder providing the write address for memory writing operation corresponding to the write signal and the write enable signal, and the read address for memory reading operation to the memory. The memory column includes an inverter and a 4-latch comprising the combination or two AND gates and one NOR gate, which are connected parallely with each other.
Abstract translation: 用于提供简单结构的锁存器的集成电路（IC）包括：用于存储输入数据的多个存储器列; 存储器，包括连接到各个存储器列的多个输出解码器; 提供与写入信号和写入使能信号相对应的用于存储器写入操作的写入地址的地址解码器和用于存储器读取操作的读取地址到存储器。 存储器列包括反相器和包括彼此并联连接的组合或两个与门和一个或非门的4锁存器。
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Patent Agency Ranking
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公开(公告)号：KR1019910007028B1
公开(公告)日：1991-09-16
申请号：KR1019880017990
申请日：1988-12-30
Applicant: 한국전자통신연구원
IPC: G06F12/00
Abstract: The pipeline processing method is that one arithmetic process is divided to a number of parts, allocated each part to different hardware, and operated them simultaneously. The momory access time of 50 n sec. for reading the command and the data is divided by three, and first two parts are used for reference time of the pipeline process. The first time is allocated for transfering the address from the CPU to the cache memory. The rest two times are allocated for transfering the data from the cash to the CPU.
Abstract translation: 流水线处理方法是将一个算术处理划分为多个部分，将每个部分分配给不同的硬件，并同时操作。 手机访问时间为50 n秒。 用于读取命令并将数据除以3，前两部分用于流水线处理的参考时间。 第一次被分配用于将地址从CPU传输到高速缓冲存储器。 其余两次被分配用于将数据从现金转移到CPU。
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