Abstract:
PURPOSE: A method for controlling a consistency of a higher-order index structure is provided to increase the performance of a search by obtaining a latch of a common mode in case that a search operation is performed, thereby preventing a delay from being generated from an insertion to a node or a lock of a deletion operation. CONSTITUTION: A route node is stored in a queue(910). A common lock is obtained(912). It is judged whether the queue is empty(914). In case that the queue isn't empty, a node is picked out from the queue and set as a current node(916). In case that the queue is empty, a lock to a reinsertion node is released. In addition, a search is terminated(938). It is judged whether a level of the current node is lower than a present level(918). A common latch is obtained(928). It is judged whether the current node is a terminal(930). In case that the current node isn't the terminal, child nodes in a range of question are put in(932). The common latch is released(936).
Abstract:
PURPOSE: A method for controlling simultaneity of high dimensional index structure is provided to perform a search of a high accuracy to objects removed for a reinsertion by performing the reinsertion to a part of object located in a node when overflowing occurred by an excess of a node capacitance. CONSTITUTION: A most suitable terminal node is searched for inserting an object(601). It is judged whether an object(e) is capable of inserting into the searched node(602). The object(e) is inserted into the searched node when the object(e) is capable of inserting into the searched node(603). A minimum boundary region is adjusted and then all process is completed(604). A node overflow is processed when the object(e) is not capable of inserting into the searched node and then all process is completed(605).
Abstract:
The sub-unit includes a local memory (1) consisting of a ROM, RAM, RTC (real time clocks) and a plurality of registers. Data latches (2a)(2b)(2c)(2d) separate addresses and data signals, and a space decoder (4) discriminates transaction call regions. A local decoder (5) outputs signals to select the respective devices of the local memory (1), and a controller (3) executes a next step when reading/writing transactions are carried out. The signal transmissions between the system bus and the local bus are rendered more efficient, because of the simplicity of the constitution.