-
-
Patent Agency Ranking
公开(公告)号：KR1020010063803A
公开(公告)日：2001-07-09
申请号：KR1019990061897
申请日：1999-12-24
Applicant: 한국전자통신연구원
IPC: G06F3/00
Abstract: PURPOSE: The MMC(Multimedia Card) supporting the video codec function is provided to support the video codec function in a small terminal while adapting the interface of the smallest MMC CONSTITUTION: The MMC has a REG_FILE(Registry File)(1), which controls the state and processing of a card, and a registry is accessed by an MMC host. An IF_DRIVER(Interface Driver)(2) drives three signals like CMD(RSP), CLK, and DAT that are inputted by a MMC_IF(Multimedia Card Interface)(3). The MMC_IF recognizes and processes each command, put together the response processing, controls the data send/receive, and provides the mean for accessing to the registry information. A V_CODEC_IF(Video Codec Interface)(4) controls the exchange of the control signal and the data send/receive between the MMC_IF and a V_CODEC(Video Codec)(6). The V_CODEC processes the video compression and recovery algorithm. A FIFO(First In First Out)(5), temporary storage when the data between the V_CODEC and MMC host is exchanged, buffers the data. The REG_FILE is a gathering of registries, which include the control information for the normal operation and whole state of the MMC.
Abstract translation: 目的：支持视频编解码功能的MMC（多媒体卡）支持小型终端中的视频编解码功能，同时适应最小MMC组合的接口：MMC具有REG_FILE（注册表文件）（1），可控制 卡的状态和处理以及注册表由MMC主机访问。 IF_DRIVER（接口驱动器）（2）驱动由MMC_IF（多媒体卡接口）（3）输入的CMD（RSP），CLK和DAT等三个信号。 MMC_IF识别和处理每个命令，将响应处理放在一起，控制数据发送/接收，并提供访问注册表信息的平均值。 V_CODEC_IF（视频编解码接口）（4）控制MMC_IF和V_CODEC（视频编解码器）（6）之间的控制信号和数据发送/接收的交换。 V_CODEC处理视频压缩和恢复算法。 FIFO（先进先出）（5），当V_CODEC和MMC主机之间的数据被交换时临时存储，缓冲数据。 REG_FILE是一个注册表集合，其中包括MMC正常运行和整个状态的控制信息。
-
公开(公告)号：KR100335374B1
公开(公告)日：2002-05-06
申请号：KR1019990061897
申请日：1999-12-24
Applicant: 한국전자통신연구원
IPC: G06F3/00
Abstract: 1. 청구범위에기재된발명이속한기술분야본 발명은멀티미디어카드(MMC)에기반한비디오코덱제어장치에관한것임. 2. 발명이해결하려고하는기술적과제본 발명은, 현재가장소형의카드인멀티미디어카드(MMC : MultiMediaCard) 형태의인터페이스를제공하는단말기가늘고있는시점에서이 인터페이스를채택하면서동시에비디오코덱기능을지원하기위한비디오코덱제어장치를제공하고자함. 3. 발명의해결방법의요지본 발명은, 멀티미디어카드(MMC) 기반의비디오코덱제어장치에있어서, 외부의멀티미디어카드(MMC) 호스트와 MMC 관련명령및 그처리결과를상호간에교환하기위한인터페이스드라이빙수단; MMC 카드의상태및 제어신호를저장하고있는저장수단; 상기 MMC 카드의상태및 제어신호를바탕으로, 상기인터페이스드라이빙수단으로부터전달된상기 MMC 호스트가제공하는 MMC 관련명령을인식하여비디오코덱제어신호를발생하고, 비디오코덱처리결과를상기인터페이스드라이빙수단으로전달하는멀티미디어인터페이싱수단; 상기비디오코덱제어신호에따라, 비디오신호를코덱(압축/복원)하는비디오신호처리수단; 및상기비디오코덱제어신호를상기비디오신호처리수단으로전달하고, 상기비디오신호처리수단에서의상기비디오코덱처리결과를저장해두었다가순차적으로상기멀티미디어인터페이싱수단으로전달하는비디오신호인터페이싱수단을포함하되, 상기멀티미디어인터페이싱수단은, 상기호스트가제공하는각종커맨드및 그결과를상기인터페이스드라이빙수단과주고받기위한커맨드응답수단; 상기커맨드에대한유효성여부를체크하기위한유효성체크수단; 상기커맨드에대한작업을수행하기위한멀티미디어카드제어수단; 및상기멀티미디어카드제어수단의제어를받으며상기비디오신호처리수단에서처리된각종데이터를상기비디오신호인터페이싱수단으로부터전달받기위한데이터전달수단을포함함. 4. 발명의중요한용도본 발명은멀티미디어카드(MMC) 등에이용됨.
-
公开(公告)号：KR1020010063814A
公开(公告)日：2001-07-09
申请号：KR1019990061911
申请日：1999-12-24
Applicant: 한국전자통신연구원
IPC: G06F7/548
Abstract: PURPOSE: A device for converting a discrete cosine and an inverse discrete cosine is provided to decrease the number of multiplications for a low electric power structure for a mobile multi media application and to perform a wave calculation in a quantization process and to satisfy a rule with respect to an accuracy of the IDCT(inverse discrete cosine transform). CONSTITUTION: In a discrete cosine transform device, a discrete cosine transform unit performs a wait calculation one time by a macro block in a quantization process. A memory stores the discrete cosine transform unit by a predetermined clock. A calculating unit performs a discrete cosine calculated unit by a predetermined clock. In an inverse discrete cosine transform device, an inverse discrete cosine transform unit performs a wait calculation one time by a macro block in a process for restoring quantization data. A memory stores the inverse discrete cosine transform unit by a predetermined clock. A calculating unit performs an inverse discrete cosine calculated unit by a predetermined clock.
Abstract translation: 目的：提供一种用于转换离散余弦和反相离散余弦的装置，以减少用于移动多媒体应用的低电力结构的乘法次数，并在量化过程中执行波计算，并满足规则 相对于IDCT（逆离散余弦变换）的精度。 构成：在离散余弦变换装置中，离散余弦变换单元在量化处理中由宏块执行一次等待计算。 存储器将离散余弦变换单元存储预定时钟。 计算单元以预定时钟执行离散余弦计算单位。 在逆离散余弦变换装置中，逆离散余弦变换单元在用于恢复量化数据的处理中由宏块执行一次等待计算。 存储器将反离散余弦变换单元存储预定时钟。 计算单元通过预定时钟执行逆离散余弦计算单元。
-
公开(公告)号：KR100365729B1
公开(公告)日：2002-12-26
申请号：KR1019990061911
申请日：1999-12-24
Applicant: 한국전자통신연구원
IPC: G06F7/548
Abstract: 본발명은이산코사인변환(DCT) 및역이산코사인변환(IDCT) 장치에관한것으로서, 휴대멀티미디어응용을위한저전력구조를위해, DCT 계산시곱셈수가줄도록웨이트연산을양자화과정에서수행하고, 표준안에서규정한 IDCT의정확도에대한규정을만족하는 18비트연산을기준으로한 이산코사인변환및 역이산코사인변환장치를제공하기위하여, 이산코사인변환(DCT) 장치에있어서, 이산코사인변환(DCT) 계산시웨이트연산을양자화과정에서매크로블록당한 번만수행하여, 8-포인트 DCT 계산시 5번의곱셈연산과 30번의덧셈연산만이필요하므로 32클럭에 8-포인트 DCT를수행하는것을특징으로하며, 영상코덱분야등에이용된다.
-
公开(公告)号：KR1020010063800A
公开(公告)日：2001-07-09
申请号：KR1019990061894
申请日：1999-12-24
Applicant: 한국전자통신연구원
IPC: G06F15/02
Abstract: PURPOSE: An integrated operator for motion estimation is provided to decrease the number of hardwares and power consumption by processing various calculations of a motion estimation process in one device. CONSTITUTION: The first input terminal inputs the first pixel value. The second input terminal inputs the second pixel value. The third input terminal inputs a discriminated signal of a subtracting calculation and an adding calculation. The fourth input terminal inputs an input carry for a rounding calculation in reverse pixel motion estimation. A logical OR calculating unit(12) calculates the value inputted from the third input terminal and the value inputted from the fourth input terminal. The first exclusive-OR calculating unit(11) calculates the second pixel value inputted from the second input terminal and the value inputted from the third input terminal. The first adding unit(13) adds the first pixel value to the calculation result of the logical OR calculating unit and the calculation result of the first exclusive-OR calculating unit. The first logical AND calculating unit(15) calculates the reverse value of the output of the first adding unit and the signal inputted from the third input terminal. The second exclusive-OR calculating unit(16) calculates the calculation result of the first adding unit and the calculation result of the first logical AND calculating unit. A register(17) receives the calculation result of the second exclusive-OR calculating unit. The second logical AND calculating unit(14) calculates the reverse value of the input of the third input terminal and the calculation result of the first adding unit and applies the result to the most significant bit of the register. The first output terminal outputs the information of the register. The second adding unit(18) calculates data inputted from the fifth input terminal, the register and the first logical AND calculating unit, respectively. The output terminal outputs the calculation result of the second adding unit and transmits the result to the fifth input terminal.
Abstract translation: 目的：提供用于运动估计的综合运算器，通过处理一个设备中的运动估计过程的各种计算来减少硬件数量和功耗。 构成：第一个输入端输入第一个像素值。 第二输入端输入第二像素值。 第三输入端输入减法运算和加法运算的鉴别信号。 第四输入端输入反向像素运动估计中的舍入计算的输入进位。 逻辑或运算单元（12）计算从第三输入端输入的值和从第四输入端输入的值。 第一异或运算单元（11）计算从第二输入端子输入的第二像素值和从第三输入端子输入的值。 第一添加单元（13）将第一像素值与逻辑或计算单元的计算结果和第一异或运算单元的计算结果相加。 第一逻辑与计算单元（15）计算第一加法单元的输出和从第三输入端输入的信号的反向值。 第二异或计算单元（16）计算第一加法单元的计算结果和第一逻辑与计算单元的计算结果。 寄存器（17）接收第二异或运算单元的计算结果。 第二逻辑与计算单元（14）计算第三输入端子的输入的反向值和第一加法单元的计算结果，并将结果应用于寄存器的最高有效位。 第一个输出端输出寄存器的信息。 第二加法单元（18）分别计算从第五输入端子，寄存器和第一逻辑与计算单元输入的数据。 输出端子输出第二加法单元的计算结果，并将结果发送给第五输入端。
-
-
-
-
-
Search Results
6
records
(took 0.018 seconds)
