公开(公告)号：KR1019940001154A

公开(公告)日：1994-01-19

申请号：KR1019920009679

申请日：1992-06-04

Applicant: 한국전자통신연구원

Inventor： 김환용 ,  김대순 ,  임순자 ,  송원철

IPC: G11C11/40

公开(公告)号：KR100092497B1

公开(公告)日：1995-12-05

申请号：KR1019920009679

申请日：1992-06-04

Applicant: 한국전자통신연구원

Inventor： 김환용 ,  김대순 ,  임순자 ,  송원철

IPC: G11C11/40

公开(公告)号：KR1019950010568B1

公开(公告)日：1995-09-19

申请号：KR1019920009679

申请日：1992-06-04

Applicant: 한국전자통신연구원

Inventor： 김환용 ,  김대순 ,  임순자 ,  송원철

IPC: G11C11/40

Abstract: The memory array structure of DRAM comprises a first memory array region, a second memory array region, a plurality of bit line pairs connected to the memory cells of the first and second memory array regions, a plurality of word lines, a plurality of sense amplifiers for sensing/amplifying the voltage difference between two bit lines, a plurality of P latches connected between bit line pairs of the first memory array region, a plurality of first equalizers for precharging the bit line pair to 1/2VDD voltage according to a first equalizer signal, a plurality of N latches connected between bit line pairs of the second memory array region, a plurality of second equalizers for precharging the bit line pair to 1/2VDD voltage according to a second equalizer signal, a plurality of barrier transistors for equalizing the bit line voltage of the first and second memory regions according to the pull-up of the first and second control signals or the third and fourth control signals.

Abstract translation: DRAM的存储器阵列结构包括第一存储器阵列区域，第二存储器阵列区域，连接到第一和第二存储器阵列区域的存储器单元的多个位线对，多个字线，多个读出放大器 用于感测/放大两个位线之间的电压差，连接在第一存储器阵列区域的位线对之间的多个P锁存器，用于根据第一均衡器将位线对预充电到1 / 2VDD电压的多个第一均衡器 信号，连接在第二存储器阵列区域的位线对之间的多个N个锁存器，用于根据第二均衡器信号将位线对预充电到1 / 2VDD电压的多个第二均衡器，多个用于均衡 根据第一和第二控制信号或第三和第四控制信号的上拉，第一和第二存储区域的位线电压。