公开(公告)号：WO1997001864A1

公开(公告)日：1997-01-16

申请号：PCT/US1996010836

申请日：1996-06-26

Applicant: ALLIEDSIGNAL INC.

Inventor： ALLIEDSIGNAL INC. ,  FORESTER, Lynn ,  CHOI, Dong, K. ,  HOSSEINI, Reza

IPC: H01L21/3105

CPC classification number: H01L21/31053

Abstract: A method for forming a gap-filled, planarization structure of dielectric materials on a substrate topography useful for forming microelectronic devices. A dielectric material is first deposited as continuous, dry dielectric layer, preferably a SOG layer. Then the dielectric layer is partially removed by chemical-mechanical polishing (CMP). The chemical and mechanical properties of the structure can be chosen by varying the composition of the SOG layer and the subsequent CMP conditions.

Abstract translation: 一种用于在用于形成微电子器件的衬底地形上形成间隙填充的介电材料平面化结构的方法。 首先将介电材料沉积为连续的干电介质层，优选为SOG层。 然后通过化学机械抛光（CMP）部分去除电介质层。 可以通过改变SOG层的组成和随后的CMP条件来选择结构的化学和机械性质。

公开(公告)号：EP0836746A1

公开(公告)日：1998-04-22

申请号：EP96923416.0

申请日：1996-06-26

Applicant: AlliedSignal Inc.

Inventor： FORESTER, Lynn ,  CHOI, Dong, K. ,  HOSSEINI, Reza

IPC: H01L21

CPC classification number: H01L21/31053

Abstract: A method for forming a gap-filled, planarization structure of dielectric materials on a substrate topography useful for forming microelectronic devices. A dielectric material is first deposited as continuous, dry dielectric layer, preferably a SOG layer. Then the dielectric layer is partially removed by chemical-mechanical polishing (CMP). The chemical and mechanical properties of the structure can be chosen by varying the composition of the SOG layer and the subsequent CMP conditions.