BIAS CIRCUIT OF EPITAXIAL WELL OF SEMICONDUCTOR INTEGRATED CIRCUIT AND INTEGRATED CIRCUIT

    公开(公告)号:JPH08250599A

    公开(公告)日:1996-09-27

    申请号:JP3789496

    申请日:1996-02-26

    Inventor: NATAARE AIETSURO

    Abstract: PROBLEM TO BE SOLVED: To positively perform reverse biasing of a parasitic diode that is formed between an epitaxial well and its adjacent region. SOLUTION: A first transistor T1 and a second transistor T2 that operates in reverse phase to the transistor T1 are provided, and the first transistor T1 is connected between a power supply and an epitaxial well, when the power supply voltage is positive. On the other hand, when the transistor T2 is cut off and the power supply voltage is negative, the second transistor T2 is connected between the epitaxial well and a ground potential GND for saturated state, thus retaining the epitaxial well at a ground voltage which is the highest voltage in a device.

    LIMITER CIRCUIT
    2.
    发明专利

    公开(公告)号:JPH07202606A

    公开(公告)日:1995-08-04

    申请号:JP19427394

    申请日:1994-08-18

    Abstract: PURPOSE: To stabilize an open ring device by reducing its gain and to smoothly reduce a load current independently of the magnitude of its increase by introducing a feedback circuit block. CONSTITUTION: A limiter circuit for a maximum current to be passed from a power transistor(TR) T'p to a load ZL connected to the TR T'p is provided with a feedback circuit block 2 in addition to a deviation amplifier 1', a driver stage P' and a detecting means Rs for a load current IL. The block 2 is connected between the control terminal of the TR T'p and a current generator in the amplifier 1'.

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