公开(公告)号：EP4415266A1

公开(公告)日：2024-08-14

申请号：EP23195920.6

申请日：2023-09-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sharma, Santosh ,  Soh, Mei Yu

IPC: H03K19/017 ,  H03K19/0944

CPC classification number: H03K19/01714 ,  H03K19/09443

Abstract: A GaN logic circuit (210) may include an input node (IN) receiving an input voltage, a first pull up transistor (218) pulling up an output voltage (OUT) in response to the input voltage (IN), and a first depletion mode transistor (220) having a first gate (G1) to which a first gate voltage (VG1) is applied and a second gate (G2) to which a second gate voltage (VG2) is applied. The first depletion mode transistor (220) may control the first pull up transistor (218) in response to a gate voltage difference (VG1 - VG2) between the first gate voltage (VG1) and the second gate voltage (VG2). The logic device may further include a capacitor (216) having a first end coupled to the first depletion mode transistor and a second end coupled to the first pull up transistor.

公开(公告)号：EP4386843A1

公开(公告)日：2024-06-19

申请号：EP23198237.2

申请日：2023-09-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sharma, Santosh ,  Kantarovsky, Johnatan Avraham ,  Krishnasamy, Rajendran

IPC: H01L27/02

CPC classification number: H01L29/1066 ,  H01L29/404 ,  H01L29/2003 ,  H01L29/7786

Abstract: An integrated circuit (IC) having a high voltage semiconductor device with a plurality of field plates between the gate and drain. The IC further includes a biasing circuit electrically coupled to each of the plurality of field plates, the biasing circuit including a plurality of high voltage depletion mode transistors, each having a pinch off voltage. The high voltage depletion mode transistors may have different pinch off voltages, and each of the field plates are each independently biased by a different one of the high voltage depletion mode transistors.

公开(公告)号：EP4354733A3

公开(公告)日：2024-05-29

申请号：EP23196216.8

申请日：2023-09-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sharma, Santosh

IPC: H03K17/16 ,  H03K17/687

CPC classification number: H03K17/162 ,  H03K17/165 ,  H03K17/163 ,  H03K17/168 ,  H03K17/6871 ,  H03K2017/687520130101

Abstract: Disclosed are circuits for controlling slew rate of a transistor during switching. Each circuit includes a first transistor (e.g., a gallium nitride (GaN)-based high electron mobility transistor (HEMT) or metal-insulator-semiconductor HEMT (MISHEMT)), a capacitor, and a second transistor. The first transistor includes a first gate connected to a pad for receiving a pulse-width modulation (PWM) signal, a first drain region connected to a first plate of the capacitor, and a first source region. The second transistor includes a second gate connected to a second plate of the capacitor, a second drain region, and a second source region and is connected to both the pad and the first transistor. The connection between the first and second transistors varies depending on whether the first transistor is an enhancement or depletion mode device and on whether the slew rate control is employed for on state or off state switching.

公开(公告)号：EP4401147A1

公开(公告)日：2024-07-17

申请号：EP23203730.9

申请日：2023-10-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sharma, Santosh ,  Pandey, Shesh Mani ,  Krishnasamy, Rajendran

IPC: H01L29/778 ,  H01L21/336 ,  H01L29/423 ,  H01L29/10 ,  H01L29/417 ,  H01L29/20

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/1066 ,  H01L29/42376 ,  H01L29/41766 ,  H01L29/66462

Abstract: A transistor on a substrate (101) includes a barrier layer (103) above the substrate and a multi-gate structure on the barrier layer. The multi-gate structure includes a primary gate (140) and a secondary gate (130). The secondary gate has opposing sidewalls, opposing end walls and a top surface. The primary gate includes essentially vertically-oriented first portions (140.1) on the barrier layer positioned laterally adjacent to opposing sidewalls (130.1), respectively, of the secondary gate. Optionally, the primary gate also includes an essentially horizontally-oriented second portion (140.2) on the top surface (130.2) of the secondary gate and/or essentially vertically-oriented third portions on the opposing end walls, respectively. The secondary gate can be a floating gate. Also disclosed is a method of forming the same.

公开(公告)号：EP4386859A1

公开(公告)日：2024-06-19

申请号：EP23204762.1

申请日：2023-10-20

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sharma, Santosh ,  Levy, Mark D.

IPC: H01L29/778 ,  H01L29/10 ,  H01L27/06 ,  H01L29/417 ,  H01L29/20

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/1066 ,  H01L29/41766 ,  H01L27/0605 ,  H01L27/085 ,  H01L21/8252

Abstract: A disclosed structure includes an enhancement mode high electron mobility transistor (HEMT). The HEMT includes a barrier layer (103) with a thick portion (103T) positioned laterally between thin portions (103t) and a gate. The gate includes a semiconductor layer (132) (e.g., a P-type III-V semiconductor layer) on the thick portion of the barrier layer and having a thick portion (132T) positioned laterally between thin portions (132t). The gate also includes a gate conductor layer (133) on and narrower than the thick portion of the semiconductor layer, so end walls of the gate are stepped. Thin portions of the barrier layer near these end walls minimize or eliminate charge build up in a channel layer below. To block current paths around the gate, isolation regions can be below the thin portions of the barrier layer offset from the semiconductor layer. The structure can further include alternating e-mode and d-mode HEMTs. Also disclosed are associated method embodiments.

公开(公告)号：EP4354733A2

公开(公告)日：2024-04-17

申请号：EP23196216.8

申请日：2023-09-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sharma, Santosh

IPC: H03K17/16 ,  H03K17/687

CPC classification number: H03K17/162 ,  H03K17/165 ,  H03K17/163 ,  H03K17/168 ,  H03K17/6871 ,  H03K2017/687520130101

Abstract: Disclosed are circuits for controlling slew rate of a transistor during switching. Each circuit includes a first transistor (e.g., a gallium nitride (GaN)-based high electron mobility transistor (HEMT) or metal-insulator-semiconductor HEMT (MISHEMT)), a capacitor, and a second transistor. The first transistor includes a first gate connected to a pad for receiving a pulse-width modulation (PWM) signal, a first drain region connected to a first plate of the capacitor, and a first source region. The second transistor includes a second gate connected to a second plate of the capacitor, a second drain region, and a second source region and is connected to both the pad and the first transistor. The connection between the first and second transistors varies depending on whether the first transistor is an enhancement or depletion mode device and on whether the slew rate control is employed for on state or off state switching.