公开(公告)号：EP4421872A1

公开(公告)日：2024-08-28

申请号：EP23204516.1

申请日：2023-10-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Pandey, Shesh Mani ,  Shanbhag, Kaustubh ,  Krishnasamy, Rajendran ,  Holt, Judson R.

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/336 ,  H01L29/16

CPC classification number: H01L29/7835 ,  H01L29/66659 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/665 ,  H01L29/16

Abstract: Disclosed are embodiments of a structure including a semiconductor layer and a device, which has a well region within the semiconductor layer and at least one porous region within and shallower in depth than the well region. In some embodiments, the device can be a field effect transistor (FET) (e.g., a laterally diffused metal oxide semiconductor field effect transistor (LDMOSFETs)) with a drain drift region that extends through the well region around the porous region(s) to a drain region. The porous region(s) can modify the electric field in this drain drift region, thereby improving device performance. Embodiments can vary with regard to the number, size, shape, configuration, etc. of the porous region(s) within the well region. Also disclosed herein are method embodiments for forming the semiconductor structure.

公开(公告)号：EP4376092A1

公开(公告)日：2024-05-29

申请号：EP23201745.9

申请日：2023-10-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Lydon-Nuhfer, Megan ,  Shank, Steven M. ,  Vallett, Aaron L. ,  Abou-Khalil, Michel ,  McTaggart, Sarah A. ,  Krishnasamy, Rajendran

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/306 ,  H01L29/04

CPC classification number: H01L29/78 ,  H01L29/4236 ,  H01L29/045 ,  H01L21/30608 ,  H01L29/66621

Abstract: An integrated circuit (IC) structure includes a V-shaped cavity in a semiconductor substrate. A source region and a drain region are on opposing sides of the V-shaped cavity. A gate structure includes a gate dielectric layer, spacers, and a gate electrode on the gate dielectric layer between the spacers. The gate structure is fully within the V-shaped cavity. The IC structure provides a switch that finds advantageous application as part of a low noise amplifier. The IC structure provides a smaller gate width, decreased capacitance, increased gain and increased radio frequency (RF) performance compared to planar devices or devices without the gate structure fully within V-shaped cavity.

公开(公告)号：EP4401137A1

公开(公告)日：2024-07-17

申请号：EP23192846.6

申请日：2023-08-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Karalkar, Sagar Premnath ,  Gebreselasie, Ephrem G. ,  Krishnasamy, Rajendran ,  Gauthier, Robert J. ,  Mitra, Souvick

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0262 ,  H02H9/046 ,  H01L27/0259

Abstract: The disclosure provides a structure including an n-type well over an n-type deep well and between a pair of p-type wells for electrostatic discharge (ESD) protection. The structure may include a p-type deep well over a substrate, a first n-type well over the p-type deep well, and a pair of p-type wells over the p-type deep well. The pair of p-type wells are each adjacent opposite horizontal ends of the n-type well. A pair of second n-type wells are over the p-type deep well and adjacent one of the pair of p-type wells. Each p-type well is horizontally between the first n-type well and one of the second n-type wells.

公开(公告)号：EP4386843A1

公开(公告)日：2024-06-19

申请号：EP23198237.2

申请日：2023-09-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sharma, Santosh ,  Kantarovsky, Johnatan Avraham ,  Krishnasamy, Rajendran

IPC: H01L27/02

CPC classification number: H01L29/1066 ,  H01L29/404 ,  H01L29/2003 ,  H01L29/7786

Abstract: An integrated circuit (IC) having a high voltage semiconductor device with a plurality of field plates between the gate and drain. The IC further includes a biasing circuit electrically coupled to each of the plurality of field plates, the biasing circuit including a plurality of high voltage depletion mode transistors, each having a pinch off voltage. The high voltage depletion mode transistors may have different pinch off voltages, and each of the field plates are each independently biased by a different one of the high voltage depletion mode transistors.

公开(公告)号：EP4300590A1

公开(公告)日：2024-01-03

申请号：EP22198916.3

申请日：2022-09-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jain, Vibhor ,  Raghunathan, Uppili S. ,  Liu, Qizhi ,  Ngu, Yves T. ,  Raman, Ajay ,  Krishnasamy, Rajendran ,  Joseph, Alvin J.

IPC: H01L29/732 ,  H01L21/331 ,  H01L29/08 ,  H01L29/06

Abstract: A structure comprising: a collector; a base over the collector; and an emitter over the base, the emitter comprising at least one stepped feature over the base.

公开(公告)号：EP4297078A1

公开(公告)日：2023-12-27

申请号：EP22205243.3

申请日：2022-11-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： He, Zhong-Xiang ,  Hazbun, Ramsey ,  Krishnasamy, Rajendran ,  Kantarovsky, Johnatan Avraham ,  Abou-Khalil, Michel ,  Rassel, Richard

IPC: H01L23/367 ,  H01L23/373 ,  H01L29/06 ,  H01L29/417 ,  H01L29/778

Abstract: A semiconductor device, comprising: a substrate; a semiconductor layer over the substrate; a device layer over the semiconductor layer, the device layer comprising a first ohmic contact and a second ohmic contact; and heat dissipating structures at least through the substrate and the semiconductor layer, wherein the heat dissipating structures are between the first ohmic contact and the second ohmic contact.

公开(公告)号：EP4404269A1

公开(公告)日：2024-07-24

申请号：EP23192844.1

申请日：2023-08-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Pandey, Shesh Mani ,  Krishnasamy, Rajendran

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7835 ,  H01L29/1045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66659

Abstract: Disclosed are embodiments of a semiconductor structure including a semiconductor device with an active device region and, within the active device region, porous semiconductor material adjacent to an isolation structure. In some embodiments, the semiconductor device can be a laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET). The LDMOSFET can include an active device region, a well region within the active device region and, within the well region, an isolation structure, a porous region immediately adjacent to the isolation structure, and a drain drift region that borders the isolation structure (e.g., between a channel region and a drain region). The porous region can modify the electric field in the drain drift region around the isolation structure and, as a result, can improve both drain-to-source breakdown voltage (BVdss) and transconductance (Gm) of the device. Also disclosed are method embodiments for forming the semiconductor structure.

公开(公告)号：EP4401147A1

公开(公告)日：2024-07-17

申请号：EP23203730.9

申请日：2023-10-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sharma, Santosh ,  Pandey, Shesh Mani ,  Krishnasamy, Rajendran

IPC: H01L29/778 ,  H01L21/336 ,  H01L29/423 ,  H01L29/10 ,  H01L29/417 ,  H01L29/20

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/1066 ,  H01L29/42376 ,  H01L29/41766 ,  H01L29/66462

Abstract: A transistor on a substrate (101) includes a barrier layer (103) above the substrate and a multi-gate structure on the barrier layer. The multi-gate structure includes a primary gate (140) and a secondary gate (130). The secondary gate has opposing sidewalls, opposing end walls and a top surface. The primary gate includes essentially vertically-oriented first portions (140.1) on the barrier layer positioned laterally adjacent to opposing sidewalls (130.1), respectively, of the secondary gate. Optionally, the primary gate also includes an essentially horizontally-oriented second portion (140.2) on the top surface (130.2) of the secondary gate and/or essentially vertically-oriented third portions on the opposing end walls, respectively. The secondary gate can be a floating gate. Also disclosed is a method of forming the same.

公开(公告)号：EP4391055A1

公开(公告)日：2024-06-26

申请号：EP23198265.3

申请日：2023-09-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Karalkar, Sagar Premnath ,  Gebreselasie, Ephrem ,  Krishnasamy, Rajendran ,  Gauthier, Robert J. ,  Mitra, Souvick

IPC: H01L27/02

CPC classification number: H01L27/0248

Abstract: Structures for an electrostatic discharge protection device and methods of forming same. The structure comprises a first well and a second well in the semiconductor substrate. The first and second wells have a first conductivity type. The structure further comprises a third well and a fourth well in the semiconductor substrate. The third and fourth wells have a second conductivity type, the third well includes a portion that overlaps with the first well, and the fourth well includes a portion that overlaps with the second well.

公开(公告)号：EP4383334A1

公开(公告)日：2024-06-12

申请号：EP23197836.2

申请日：2023-09-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Krishnasamy, Rajendran ,  Ellis-Monaghan, John J. ,  Adusumilli, Siva P. ,  Hazbun, Ramsey M.

IPC: H01L27/146 ,  H01L31/105 ,  H01L31/028 ,  H01L31/0352

CPC classification number: H01L31/105 ,  H01L31/028 ,  H01L31/035281 ,  H01L27/1461 ,  H01L27/1446 ,  H01L27/14612

Abstract: A photodiode and a related method of manufacture are disclosed. The photodiode (100) includes a transfer gate (122) and a floating diffusion (124) adjacent to the transfer gate. In addition, the photodiode includes an upper terminal (112); an intrinsic semiconductor region (114) in contact with the upper terminal, the intrinsic semiconductor region in a trench (130) in a substrate (132) adjacent to the transfer gate; and a lower terminal (116) in contact with the intrinsic semiconductor region. An insulator layer (140) is along an entirety of a sidewall (142) of the intrinsic semiconductor region and between the intrinsic semiconductor region and the transfer gate. A p-type well (154, 156) may also optionally be between the insulator layer and the transfer gate.