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公开(公告)号：GB2547397A
公开(公告)日：2017-08-16
申请号：GB201709198
申请日：2015-11-13
Applicant: IBM
Inventor： ROBERT SONNELITTER III , EKATERINA AMBROLADZE , ARTHUR O'NEILL JR , MICHAEL FEE , DEANNA POSTLES DUNN BERGER
IPC: G06F12/0815 , G06F12/084
Abstract: Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration
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公开(公告)号：GB2576860B
公开(公告)日：2020-08-05
申请号：GB201918172
申请日：2018-06-14
Applicant: IBM
Inventor： PATRICK JAMES MEANEY , BARRY TRAGER , GLENN DAVID GILDA , ARTHUR O'NEILL JR
Abstract: Systems, methods, and computer-readable media are disclosed for performing reduced latency error decoding using a reduced latency symbol error correction decoder that utilizes enumerated parallel multiplication in lieu of division and replaces general multiplication with constant multiplication. The use of parallel multiplication in lieu of division can provide reduced latency and replacement of general multiplication with constant multiplication allows for logic reduction. In addition, the reduced symbol error correction decoder can utilize decode term sharing which can yield a further reduction in decoder logic and a further latency improvement.
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公开(公告)号：GB2547397B
公开(公告)日：2017-11-29
申请号：GB201709198
申请日：2015-11-13
Applicant: IBM
Inventor： ROBERT SONNELITTER III , EKATERINA AMBROLADZE , ARTHUR O'NEILL JR , MICHAEL FEE , DEANNA POSTLES DUNN BERGER
IPC: G06F12/0815 , G06F12/084
Abstract: Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration.
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公开(公告)号：GB2576860A
公开(公告)日：2020-03-04
申请号：GB201918172
申请日：2018-06-14
Applicant: IBM
Inventor： PATRICK JAMES MEANEY , BARRY TRAGER , GLENN DAVID GILDA , ARTHUR O'NEILL JR
Abstract: Systems, methods, and computer-readable media are disclosed for performing reduced latency error decoding using a reduced latency symbol error correction decoder that utilizes enumerated parallel multiplication in lieu of division and replaces general multiplication with constant multiplication. The use of parallel multiplication in lieu of division can provide reduced latency and replacement of general multiplication with constant multiplication allows for logic reduction. In addition, the reduced symbol error correction decoder can utilize decode term sharing which can yield a further reduction in decoder logic and a further latency improvement.
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